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| hcs08 microcontrollers freescale.com MC9S08QD4 data sheet MC9S08QD4 rev. 1 9/2006 4 datasheet u .com
4 datasheet u .com 8-bit hcs08 central processor unit (cpu) 16-mhz hcs08 cpu (central processor unit) hc08 instruction set with added bgnd instruction background debugging system breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) support for up to 32 interrupt/reset sources memory flash read/program/erase over full operating voltage and temperature 4,096 bytes flash 256 bytes ram power-saving modes wait plus three stops clock source options ics ?internal clock source module (ics) containing a frequency-locked-loop (fll) controlled by internal or external reference. precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage. system protection watchdog computer operating properly (cop) reset with option to run from dedicated 32-khz internal clock source or bus clock low-voltage detection with reset or interrupt illegal opcode detection with reset illegal address detection with reset (some devices don t have illegal addresses) flash block protect peripherals adc ?4-channel, 10-bit analog-to-digital converter with automatic compare function, asynchronous clock source, temperature sensor and internal bandgap reference channel. adc is hardware triggerable using the rti counter. tim1 ?2-channel timer/pulse-width modulator; each channel can be used for input capture, output compare, buffered edge-aligned pwm, or buffered center-aligned pwm tim2 ?1-channel timer/pulse-width modulator; each channel can be used for input capture, output compare, buffered edge-aligned pwm, or buffered center-aligned pwm kbi ?4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes input/output 4 general-purpose input/output (i/o) pins, one input-only pin and one output-only pin. outputs 10 ma each, 60 ma maximum for package. software selectable pullups on ports when used as input software selectable slew rate control and drive strength on ports when used as output internal pullup on reset and irq pin to reduce customer system cost development support single-wire background debug interface package options 8-pin pdip 8-pin narrow body small outline integrated circuit (soic) package MC9S08QD4 features 4 datasheet u .com 4 datasheet u .com MC9S08QD4 data sheet MC9S08QD4 rev. 1 9/2006 4 datasheet u .com revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. revision number revision date description of changes 1 15 sep 06 initial public release this product incorporates superflash ? technology licensed from sst. freescale and the freescale logo are trademarks of freescale semiconductor, inc. freescale semiconductor, inc., 2006. all rights reserved. 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 7 list of chapters chapter 1 device overview ...................................................................... 17 chapter 2 external signal description .................................................... 21 chapter 3 modes of operation ................................................................. 27 chapter 4 memory map and register definition .................................... 33 chapter 5 resets, interrupts, and general system control.................. 51 chapter 6 parallel input/output control.................................................. 67 chapter 7 central processor unit (s08cpuv2) ...................................... 73 chapter 8 analog-to-digital converter (adc10v1) ................................ 93 chapter 9 internal clock source (s08icsv1)........................................ 121 chapter 10 keyboard interrupt (s08kbiv2) ............................................ 129 chapter 11 timer/pulse-width modulator (s08tpmv2) ......................... 137 chapter 12 development support ........................................................... 153 appendix a electrical characteristics...................................................... 167 appendix b ordering information and mechanical drawings................ 185 4 datasheet u .com 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 9 contents section number title page chapter 1 device overview 1.1 introduction ................................................................................................................ .....................17 1.1.1 mcu block diagram ........................................................................................................1 8 1.2 system clock distribution ................................................................................................... ...........19 chapter 2 external signal description 2.1 device pin assignment ....................................................................................................... ............21 2.2 recommended system connections .............................................................................................. .21 2.2.1 power ..................................................................................................................... ...........22 2.2.2 oscillator ................................................................................................................ ...........23 2.2.3 reset (input only) ........................................................................................................ .....23 2.2.4 background / mode select (bkgd/ms) ..........................................................................23 2.2.5 general-purpose i/o and peripheral ports ........................................................................24 chapter 3 modes of operation 3.1 introduction ................................................................................................................ .....................27 3.2 features .................................................................................................................... .......................27 3.3 run mode .................................................................................................................... ....................27 3.4 active background mode ...................................................................................................... ..........27 3.5 wait mode ................................................................................................................... ....................28 3.6 stop modes .................................................................................................................. ....................28 3.6.1 stop2 mode ................................................................................................................ .......29 3.6.2 stop3 mode ................................................................................................................ .......30 3.6.3 active bdm enabled in stop mode .................................................................................30 3.6.4 lvd enabled in stop mode ..............................................................................................31 3.6.5 on-chip peripheral modules in stop modes ....................................................................31 chapter 4 memory map and register definition 4.1 MC9S08QD4 memory map ........................................................................................................ ....33 4.2 reset and interrupt vector assignments ...................................................................................... ...34 4.3 register addresses and bit assignments ...................................................................................... ..35 4.4 ram ......................................................................................................................... .......................38 4.5 flash ....................................................................................................................... .....................39 4.5.1 features .................................................................................................................. ...........39 4.5.2 program and erase times .................................................................................................39 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 10 freescale semiconductor section number title page 4.5.3 program and erase command execution .........................................................................40 4.5.4 burst program execution ..................................................................................................4 1 4.5.5 access errors ............................................................................................................. .......43 4.5.6 flash block protection ..................................................................................................43 4.5.7 vector redirection ........................................................................................................ ....44 4.6 security .................................................................................................................... ........................44 4.7 flash registers and control bits ............................................................................................ .....46 4.7.1 flash clock divider register (fcdiv) ........................................................................46 4.7.2 flash options register (fopt and nvopt) ................................................................47 4.7.3 flash con?uration register (fcnfg) ........................................................................48 4.7.4 flash protection register (fprot and nvprot) .......................................................48 4.7.5 flash status register (fstat) ......................................................................................49 4.7.6 flash command register (fcmd) ...............................................................................50 chapter 5 resets, interrupts, and general system control 5.1 introduction ................................................................................................................ .....................51 5.2 features .................................................................................................................... .......................51 5.3 mcu reset ................................................................................................................... ...................51 5.4 computer operating properly (cop) watchdog .............................................................................52 5.5 interrupts .................................................................................................................. .......................53 5.5.1 interrupt stack frame ..................................................................................................... ..54 5.5.2 external interrupt request (irq) pin ...............................................................................54 5.5.3 interrupt vectors, sources, and local masks ....................................................................55 5.6 low-voltage detect (lvd) system ............................................................................................. ...56 5.6.1 power-on reset operation ...............................................................................................57 5.6.2 lvd reset operation ....................................................................................................... .57 5.6.3 lvd interrupt operation ................................................................................................... 57 5.6.4 low-voltage warning (lvw) ...........................................................................................57 5.7 real-time interrupt (rti) ................................................................................................... ............57 5.8 reset, interrupt, and system control registers and control bits ...................................................58 5.8.1 interrupt pin request status and control register (irqsc) ............................................58 5.8.2 system reset status register (srs) .................................................................................59 5.8.3 system background debug force reset register (sbdfr) ............................................60 5.8.4 system options register 1 (sopt1) ................................................................................61 5.8.5 system options register 2 (sopt2) ................................................................................62 5.8.6 system device identi?ation register (sdidh, sdidl) ................................................62 5.8.7 system real-time interrupt status and control register (srtisc) ................................63 5.8.8 system power management status and control 1 register (spmsc1) ...........................64 5.8.9 system power management status and control 2 register (spmsc2) ...........................65 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 11 section number title page chapter 6 parallel input/output control 6.1 port data and data direction ................................................................................................ ..........67 6.2 pin control ?pullup, slew rate and drive strength ....................................................................68 6.3 pin behavior in stop modes .................................................................................................. ..........69 6.4 parallel i/o registers ...................................................................................................... .................69 6.4.1 port a registers .......................................................................................................... ......69 6.4.2 port a control registers .................................................................................................. .70 chapter 7 central processor unit (s08cpuv2) 7.1 introduction ................................................................................................................ .....................73 7.1.1 features .................................................................................................................. ...........73 7.2 programmer s model and cpu registers .......................................................................................7 4 7.2.1 accumulator (a) ........................................................................................................... ....74 7.2.2 index register (h:x) ...................................................................................................... ...74 7.2.3 stack pointer (sp) ........................................................................................................ .....75 7.2.4 program counter (pc) ...................................................................................................... 75 7.2.5 condition code register (ccr) .......................................................................................75 7.3 addressing modes ............................................................................................................ ...............77 7.3.1 inherent addressing mode (inh) .....................................................................................77 7.3.2 relative addressing mode (rel) .....................................................................................77 7.3.3 immediate addressing mode (imm) ................................................................................77 7.3.4 direct addressing mode (dir) ........................................................................................77 7.3.5 extended addressing mode (ext) ..................................................................................78 7.3.6 indexed addressing mode ................................................................................................78 7.4 special operations .......................................................................................................... .................79 7.4.1 reset sequence ............................................................................................................ .....79 7.4.2 interrupt sequence ........................................................................................................ ....79 7.4.3 wait mode operation ....................................................................................................... .80 7.4.4 stop mode operation ....................................................................................................... .80 7.4.5 bgnd instruction .......................................................................................................... ...81 7.5 hcs08 instruction set summary ............................................................................................... .....82 chapter 8 analog-to-digital converter (adc10v1) 8.1 introduction ................................................................................................................ .....................93 8.1.1 module con?urations .....................................................................................................9 5 8.1.2 features .................................................................................................................. ...........97 8.1.3 block diagram ............................................................................................................. .....97 8.2 external signal description ................................................................................................. ...........98 8.2.1 analog power (v ddad ) ....................................................................................................99 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 12 freescale semiconductor section number title page 8.2.2 analog ground (v ssad ) ...................................................................................................99 8.2.3 voltage reference high (v refh ) .....................................................................................99 8.2.4 voltage reference low (v refl ) .......................................................................................99 8.2.5 analog channel inputs (adx) ..........................................................................................99 8.3 register de?ition .......................................................................................................... ................99 8.3.1 status and control register 1 (adcsc1) ........................................................................99 8.3.2 status and control register 2 (adcsc2) ......................................................................101 8.3.3 data result high register (adcrh) .............................................................................102 8.3.4 data result low register (adcrl) ..............................................................................102 8.3.5 compare value high register (adccvh) ....................................................................103 8.3.6 compare value low register (adccvl) .....................................................................103 8.3.7 con?uration register (adccfg) ................................................................................103 8.3.8 pin control 1 register (apctl1) ..................................................................................105 8.3.9 pin control 2 register (apctl2) ..................................................................................106 8.3.10 pin control 3 register (apctl3) ..................................................................................107 8.4 functional description ...................................................................................................... ............108 8.4.1 clock select and divide control ....................................................................................108 8.4.2 input select and pin control ...........................................................................................109 8.4.3 hardware trigger .......................................................................................................... ..109 8.4.4 conversion control ........................................................................................................ .109 8.4.5 automatic compare function .........................................................................................112 8.4.6 mcu wait mode operation ............................................................................................112 8.4.7 mcu stop3 mode operation ..........................................................................................112 8.4.8 mcu stop1 and stop2 mode operation .........................................................................113 8.5 initialization information .................................................................................................. ............113 8.5.1 adc module initialization example .............................................................................113 8.6 application information ..................................................................................................... ...........115 8.6.1 external pins and routing ..............................................................................................115 8.6.2 sources of error .......................................................................................................... ....117 chapter 9 internal clock source (s08icsv1) 9.1 introduction ................................................................................................................ ...................121 9.1.1 ics con?uration information .......................................................................................121 9.1.2 features .................................................................................................................. .........123 9.1.3 modes of operation ........................................................................................................ 123 9.1.4 block diagram ............................................................................................................. ...123 9.2 external signal description ................................................................................................. .........124 9.3 register de?ition .......................................................................................................... ..............124 9.3.1 ics control register 1 (icsc1) .....................................................................................124 9.3.2 ics control register 2 (icsc2) .....................................................................................125 9.3.3 ics trim register (icstrm) .........................................................................................125 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 13 section number title page 9.3.4 ics status and control (icssc) .....................................................................................126 9.4 functional description ...................................................................................................... ............126 9.4.1 operational modes ......................................................................................................... .126 9.4.2 mode switching ............................................................................................................ ..127 9.4.3 bus frequency divider ...................................................................................................12 7 9.4.4 low power bit usage .....................................................................................................12 8 9.4.5 internal reference clock ................................................................................................12 8 9.4.6 fixed frequency clock ...................................................................................................12 8 chapter 10 keyboard interrupt (s08kbiv2) 10.1 introduction ............................................................................................................... ....................129 10.1.1 features ................................................................................................................. ..........131 10.1.2 modes of operation ....................................................................................................... .131 10.1.3 block diagram ............................................................................................................ ....131 10.2 external signal description ................................................................................................ ..........132 10.3 register de?ition ......................................................................................................... ...............133 10.3.1 kbi status and control register (kbisc) .....................................................................133 10.3.2 kbi pin enable register (kbipe) ..................................................................................133 10.3.3 kbi edge select register (kbies) ................................................................................134 10.4 functional description ..................................................................................................... .............134 10.4.1 edge only sensitivity .................................................................................................... .135 10.4.2 edge and level sensitivity ..............................................................................................1 35 10.4.3 kbi pullup/pulldown resistors ......................................................................................135 10.4.4 kbi initialization ....................................................................................................... .....135 chapter 11 timer/pulse-width modulator (s08tpmv2) 11.1 introduction ............................................................................................................... ....................137 11.1.1 tpm2 con?uration information ...................................................................................137 11.1.2 tclk1 and tclk2 con?uration information .............................................................137 11.1.3 features ................................................................................................................. ..........139 11.1.4 block diagram ............................................................................................................ ....139 11.2 external signal description ................................................................................................ ..........141 11.2.1 external tpm clock sources ..........................................................................................141 11.2.2 tpmxchn ?tpmx channel n i/o pins .......................................................................141 11.3 register de?ition ......................................................................................................... ...............141 11.3.1 timer status and control register (tpmxsc) ...............................................................142 11.3.2 timer counter registers (tpmxcnth:tpmxcntl) ...................................................143 11.3.3 timer counter modulo registers (tpmxmodh:tpmxmodl) ..................................144 11.3.4 timer channel n status and control register (tpmxcnsc) .........................................145 11.3.5 timer channel value registers (tpmxcnvh:tpmxcnvl) .........................................146 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 14 freescale semiconductor section number title page 11.4 functional description ..................................................................................................... .............147 11.4.1 counter .................................................................................................................. ..........147 11.4.2 channel mode selection .................................................................................................14 8 11.4.3 center-aligned pwm mode ...........................................................................................150 11.5 tpm interrupts ............................................................................................................. .................151 11.5.1 clearing timer interrupt flags .......................................................................................151 11.5.2 timer over?w interrupt description ............................................................................151 11.5.3 channel event interrupt description ..............................................................................152 11.5.4 pwm end-of-duty-cycle events ...................................................................................152 chapter 12 development support 12.1 introduction ............................................................................................................... ....................153 12.1.1 module con?uration .....................................................................................................1 53 12.1.2 features ................................................................................................................. ..........154 12.2 background debug controller (bdc) .......................................................................................... 154 12.2.1 bkgd pin description ...................................................................................................15 5 12.2.2 communication details ..................................................................................................15 5 12.2.3 bdc commands ............................................................................................................. 159 12.2.4 bdc hardware breakpoint .............................................................................................161 12.3 register de?ition ......................................................................................................... ...............161 12.3.1 bdc registers and control bits .....................................................................................162 12.3.2 system background debug force reset register (sbdfr) ..........................................164 appendix a electrical characteristics a.1 introduction ................................................................................................................ ...................167 a.2 absolute maximum ratings .................................................................................................... ......167 a.3 thermal characteristics ..................................................................................................... ............168 a.4 esd protection and latch-up immunity ......................................................................................16 9 a.5 dc characteristics .......................................................................................................... ...............169 a.6 supply current characteristics .............................................................................................. ........176 a.7 internal clock source characteristics ....................................................................................... ....178 a.8 ac characteristics .......................................................................................................... ...............180 a.8.1 control timing ............................................................................................................ ...180 a.8.2 timer/pwm (tpm) module timing ..............................................................................181 a.9 adc characteristics ......................................................................................................... .............182 a.10 flash specifications ....................................................................................................... ............183 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 15 section number title page appendix b ordering information and mechanical drawings b.1 ordering information ........................................................................................................ ............185 b.1.1 device numbering scheme ............................................................................................185 b.2 mechanical drawings ......................................................................................................... ...........185 4 datasheet u .com 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 17 chapter 1 device overview 1.1 introduction the MC9S08QD4 is a member of the low-cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced hcs08 core and are available with a variety of modules, memory sizes, memory types, and package types. 4 datasheet u .com chapter 1 device overview MC9S08QD4 data sheet, rev. 1 18 freescale semiconductor 1.1.1 mcu block diagram figure 1-1. MC9S08QD4 block diagram notes: 1 port pins are software con?urable with pullup device if input port. 2 port pins are software con?urable for output drive strength. 3 port pins are software con?urable for output slew rate control. 4 irq contains a software con?urable (irqpdd) pullup/pulldown device if pta5 enabled as irq pin function (irqpe = 1). 5 reset contains integrated pullup device if pta5 enabled as reset pin function (rstpe = 1). 6 pta5 does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 7 pta4 contains integrated pullup device if bkgd enabled (bkgdpe = 1). 8 when pin functions as kbi (kbipen = 1) and associated pin is con?ured to enable the pullup device, kbedgn can be used to recon?ure the pullup as a pulldown device. user ram hcs08 core cpu bdc 2-ch 16-bit timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management rti cop irq lvd voltage regulator port a pta5/tpm2ch0i/irq/ reset pta4/tpm2ch0o/bkgd/ms pta3/kbi1p3/tclk2/adc1p3 pta2/kbi1p2/tclk1/adc1p2 pta1/kbi1p1/tpm1ch1/adc1p1 pta0/kbi1p0/tpm1ch0/adc1p0 4-bit keyboard interrupt module (kbi) 256 bytes 16-mhz internal clock source (ics) v ss v dd v ssa v dda v refl v refh 4 analog-to-digital converter (adc) 10-bit tpm1ch0 tpm1ch1 bkgd/ms irq 4 1-ch 16-bit timer/pwm module (tpm2) tpm2ch0 user flash 4096 bytes tclk2 tclk1 4 datasheet u .com chapter 1 device overview MC9S08QD4 data sheet, rev. 1 freescale semiconductor 19 table 1-1 provides the functional versions of the on-chip modules. 1.2 system clock distribution figure 1-2 shows a simpli?d clock connection diagram. some modules in the mcu have selectable clock inputs as shown. the clock inputs to the modules indicate the clock(s) that are used to drive the module function. all memory mapped registers associated with the modules are clocked with busclk. figure 1-2. system clock distribution diagram table 1-1. versions of on-chip modules module version analog-to-digital converter (adc) 1 central processing unit (cpu) 2 internal clock source (ics) 1 keyboard interrupt (kbi) 2 timer pulse-width modulator (tpm) 2 tpm1 tpm2 cpu bdc adc flash ics icsout 2 system control logic busclk icslclk** rti ** icslclk is the alternate bdc clock source for the MC9S08QD4. 2 flash has frequency requirements for program and erase operation. see appendix a, ?lectrical characteristics . adc has min and max frequency requirements. see adc chapter and appendix a, ?lectrical characteristics . icsffclk cop tclk1 tclk2 icsirclk fixed freq clock (xclk) 4 datasheet u .com chapter 1 device overview MC9S08QD4 data sheet, rev. 1 20 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 21 chapter 2 external signal description this section describes signals that connect to package pins. it includes pinout diagrams, table of signal properties, and detailed discussions of signals. 2.1 device pin assignment figure 2-1 shows the pin assignments for the 8-pin packages. figure 2-1. 8-pin packages 2.2 recommended system connections figure 2-2 shows pin connections that are common to almost all MC9S08QD4 application systems. 8-pin assignment MC9S08QD4 dip/soic 1 2 3 4 8 7 6 5 pta0/kbi1p0/tpm1ch0/adc1p0 pta1/kbi1p1/tpm1ch1/adc1p1 pta2/kbi1p2/tclk1/adc1p2 pta3/kbi1p3/tclk2/adc1p3 v ss v dd pta4/tpm2ch0o/bkgd/ms pta5/tpm2ch0i/irq/ reset 4 datasheet u .com chapter 2 external signal description MC9S08QD4 data sheet, rev. 1 22 freescale semiconductor figure 2-2. basic system connections 2.2.1 power v dd and v ss are the primary power supply pins for the mcu. this voltage source supplies power to all i/o buffer circuitry, the adc module, and to an internal voltage regulator. the internal voltage regulator provides regulated lower-voltage source to the cpu and other internal circuitry of the mcu. typically, application systems have two separate capacitors across the power pins: a bulk electrolytic capacitor, such as a 10 f tantalum capacitor, to provide bulk charge storage for the overall system, and a bypass capacitor, such as a 0.1 f ceramic capacitor, located as near to the mcu power pins as practical to suppress high-frequency noise. v dd v ss reset optional manual reset port a v dd background header c by 0.1 f c blk 10 f + 5 v + system power i/o and peripheral interface to system application pta0/kbi1p0/tpm1ch0/adc1p0 pta1/kbi1p1/tpm1ch1/adc1p1 pta2/kbi1p2/tclk1/adc1p2 pta3/kbi1p3/tclk2/adc1p3 v dd pta4/tpm2ch0o/bkgd/ms pta5/tpm2ch0i/irq/ reset MC9S08QD4 bkgd note 2 notes: 1. reset pin can only be used to reset into user mode, you can not enter bdm using reset pin. bdm can be entered by holding ms low during por or writing a 1 to bdfr in sbdfr with ms low after issuing bdm command. 2. irq has optional internal pullup/pulldown device irq asynchronous interrupt input note 1 4 datasheet u .com chapter 2 external signal description MC9S08QD4 data sheet, rev. 1 freescale semiconductor 23 2.2.2 oscillator out of reset the mcu uses an internally generated clock provided by the internal clock source (ics) module. the internal frequency is nominally 16-mhz and the default ics settings will provide for a 4-mhz bus out of reset. for more information on the ics, see the internal clock source chapter. 2.2.3 reset (input only) after a power-on reset (por) into user mode, the pta5/tpm2ch0i/irq/ reset pin defaults to a general-purpose input port pin, pta5. setting rstpe in sopt1 con?ures the pin to be the reset input pin. once con?ured as reset, the pin will remain reset until the next por. the reset pin can be used to reset the mcu from an external source when the pin is driven low. when enabled as the reset pin (rstpe = 1), an internal pullup device is automatically enabled. after a por into active background mode, the pta5/tpm2ch0i/irq/ reset pin defaults to the reset pin. when tpm2 is con?ured for input capture, the pin will be the input capture pin tpm2ch0i. note this pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up reset pin may be as low as v dd 0.7 v. the internal gates connected to this pin are pulled to v dd . 2.2.4 background / mode select (bkgd/ms) during a power-on-reset (por) or background debug force reset (see 5.8.3, ?ystem background debug force reset register (sbdfr) for more information), the pta4/tpm2ch0o/bkgd/ms pin functions as a mode select pin. immediately after any reset, the pin functions as the background pin and can be used for background debug communication. when enabled as the bkgd/ms pin (bkgdpe = 1), an internal pullup device is automatically enabled. the background debug communication function is enabled when bkgdpe in sopt1 is set. bkgdpe is set following any reset of the mcu and must be cleared to use the pta4/tpm2ch0o/bkgd/ms pins alternative pin functions. if nothing is connected to this pin, the mcu will enter normal operating mode at the rising edge of the internal reset after a por or force bdc reset. if a debug system is connected to the 6-pin standard background debug header, it can hold bkgd/ms low during a por or immediately after issuing a background debug force reset, which will force the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communications using a custom protocol that uses 16 clock cycles of the target mcu s bdc clock per bit time. the target mcu s bdc clock could be as fast as the maximum bus clock rate, so there must never be any signi?ant capacitance connected to the bkgd/ms pin that could interfere with background serial communications. 4 datasheet u .com chapter 2 external signal description MC9S08QD4 data sheet, rev. 1 24 freescale semiconductor although the bkgd pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the bkgd pin. 2.2.5 general-purpose i/o and peripheral ports the MC9S08QD4 series of mcus support up to 4 general-purpose i/o pins, 1 input-only pin and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial i/o, adc, keyboard interrupts, etc.). on each of the MC9S08QD4 devices there is one input-only and one output-only port pin. when a port pin is con?ured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. when a port pin is con?ured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pullup device. for information about controlling these pins as general-purpose i/o pins, see the chapter 6, ?arallel input/output control . for information about how and when on-chip peripheral systems use these pins, see the appropriate chapter referenced in table 2-1 . immediately after reset, all pins that are not output-only are con?ured as high-impedance, general-purpose inputs with internal pullup devices disabled. after reset, the output-only port function is not enabled but is con?ured for low output drive strength with slew rate control enabled. the pta4 pin defaults to bkgd/ms on any reset. note to avoid extra current drain from ?ating input pins, the reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not ?at. 2.2.5.1 pin control registers to select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin control register located in the high-page register block of the memory map. the pin control registers operate independently of the parallel i/o registers and allow control of a port on an individual pin basis. 2.2.5.1.1 internal pullup enable an internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (ptxpen). the pullup device is disabled if the pin is con?ured as an output by the parallel i/o control logic or any shared peripheral function, regardless of the state of the corresponding pullup enable register bit. the pullup device is also disabled if the pin is controlled by an analog function. the kbi module and irq function when enabled for rising edge detection causes an enabled internal pull device to be con?ured as a pulldown. 4 datasheet u .com chapter 2 external signal description MC9S08QD4 data sheet, rev. 1 freescale semiconductor 25 2.2.5.2 output slew rate control slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate control registers (ptxsen). when enabled, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins that are con?ured as inputs. 2.2.5.3 output drive strength select an output pin can be selected to have high output drive strength by setting the corresponding bit in one of the drive strength select registers (ptxdsn). when high drive is selected, a pin is capable of sourcing and sinking greater current. even though every i/o pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded. drive strength selection is intended to affect the dc behavior of i/o pins. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this, the emc emissions may be affected by enabling pins as high drive. table 2-1. pin sharing priority lowest <- pin function priority -> highest reference 1 1 see the module section listed for information on modules that share these pins. port pins alternative function alternative function alternative function pta0 pta1 pta2 pta3 pta4 pta5 2 2 pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd 0.7 v. the internal gates connected to this pin are pulled to v dd . kbi1p0 kbi1p1 kbi1p2 kbi1p3 tpm2ch0o tpm2ch0i tpm1ch0 tpm1ch1 tclk1 tclk2 bkgd/ms irq adc1p0 3 adc1p1 3 adc1p2 3 adc1p3 3 reset 3 if both of these analog modules are enabled both will have access to the pin. kbi1, adc1, and tpm1 chapters kbi1, adc1, and tpm1 chapters kbi1, adc1, and tpm1 chapters kbi1, adc1, and tpm2 chapters tpm2 chapters irq 4 , and tpm2 chapters 4 see 5.8, ?eset, interrupt, and system control registers and control bits for information on con?uring the irq module. 4 datasheet u .com chapter 2 external signal description MC9S08QD4 data sheet, rev. 1 26 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 27 chapter 3 modes of operation 3.1 introduction the operating modes of the MC9S08QD4 are described in this chapter. entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 features active background mode for code development wait mode: cpu shuts down to conserve power system clocks running full voltage regulation maintained stop modes: cpu and bus clocks stopped stop2 ?partial power down of internal circuits, ram contents retained stop3 ?all internal circuits powered for fast recovery 3.3 run mode this is the normal operating mode for the MC9S08QD4. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at 0xfffe:0xffff after reset. 3.4 active background mode the active background mode functions are managed through the background debug controller (bdc) in the hcs08 core. the bdc provides the means for analyzing mcu operation during software development. active background mode is entered in any of ve ways: when the bkgd/ms pin is low at the rising edge of reset when a background command is received through the bkgd pin when a bgnd instruction is executed when encountering a bdc breakpoint 4 datasheet u .com chapter 3 modes of operation MC9S08QD4 data sheet, rev. 1 28 freescale semiconductor after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructions from the user s application program. background commands are of two types: non-intrusive commands, de?ed as commands that can be issued while the user program is running. non-intrusive commands can be issued through the bkgd pin while the mcu is in run mode; non-intrusive commands can also be executed when the mcu is in the active background mode. non-intrusive commands include: memory access commands memory-access-with-status commands bdc register access commands the background command active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: read or write cpu registers trace one user program instruction at a time leave active background mode to return to the user s application program (go) the active background mode is used to program a bootloader or user application program into the flash program memory before the mcu is operated in run mode for the ?st time. when the MC9S08QD4 is shipped from the freescale semiconductor factory, the flash program memory is erased by default unless speci?ally noted, so no program can be executed in run mode until the flash memory is initially programmed. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to chapter 12, ?evelopment support . 3.5 wait mode wait mode is entered by executing a wait instruction. upon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background command and memory-access-with-status commands are available when the mcu is in wait mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 3.6 stop modes one of two stop modes is entered upon execution of a stop instruction when the stope bit in the system option register is set. in both stop modes, all internal clocks are halted. if the stope bit is not set when 4 datasheet u .com chapter 3 modes of operation MC9S08QD4 data sheet, rev. 1 freescale semiconductor 29 the cpu executes a stop instruction, the mcu will not enter either of the stop modes and an illegal opcode reset is forced. the stop modes are selected by setting the appropriate bits in spmsc2. hcs08 devices that are designed for low voltage operation (1.8v to 3.6v) also include stop1 mode. the MC9S08QD4 device does not include stop1 mode. table 3-1 summarizes the behavior of the mcu in each of the stop modes. 3.6.1 stop2 mode the stop2 mode provides very low standby power consumption and maintains the contents of ram and the current state of all of the i/o pins. to enter stop2, the user must execute a stop instruction with stop2 selected (ppdc = 1) and stop mode enabled (stope = 1). in addition, the lvd must not be enabled to operate in stop (lvdse = 0 or lvde = 0). if the lvd is enabled in stop, then the mcu enters stop3 upon the execution of the stop instruction regardless of the state of ppdc. before entering stop2 mode, the user must save the contents of the i/o port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in ram. upon exit of stop2, these values can be restored by user software before pin latches are opened. when the mcu is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the ram. the voltage regulator is in a low-power standby state, as is the adc. upon entry into stop2, the states of the i/o pins are latched. the states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to ppdack in spmsc2. exit from stop2 is done by asserting either of the wake-up pins: reset or irq, or by an rti interrupt. irq is always an active low input when the mcu is in stop2, regardless of how it was con?ured before entering stop2. note although this irq pin is automatically con?ured as active low input, the pullup associated with the irq pin is not automatically enabled. therefore, if an external pullup is not used, the internal pullup must be enabled by setting irqpe in irqsc. upon wake-up from stop2 mode, the mcu will start up as from a power-on reset (por) except pin states remain latched. the cpu will take the reset vector. the system and all peripherals will be in their default reset states and must be initialized. table 3-1. stop mode behavior mode ppdc cpu, digital peripherals, flash ram ics adc1 regulator i/o pins rti stop2 1 off standby off disabled standby states held optionally on stop3 0 standby standby off 1 1 ics can be con?ured to run in stop3. please see the ics registers. optionally on standby states held optionally on 4 datasheet u .com chapter 3 modes of operation MC9S08QD4 data sheet, rev. 1 30 freescale semiconductor after waking up from stop2, the ppdf bit in spmsc2 is set. this ?g may be used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a logic 1 is written to ppdack in spmsc2. to maintain i/o state for pins that were con?ured as general-purpose i/o, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the register bits will assume their reset states when the i/o pin latches are opened and the i/o pins will switch to their reset states. for pins that were con?ured as peripheral i/o, the user must recon?ure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.2 stop3 mode stop3 mode is entered by executing a stop instruction under the conditions as shown in table 3-1 . the states of all of the internal registers and logic, ram contents, and i/o pin states are maintained. stop3 can be exited by asserting reset, or by an interrupt from one of the following sources: the real-time interrupt (rti), lvd, adc, irq, or the kbi. if stop3 is exited by means of the reset pin, then the mcu is reset and operation will resume after taking the reset vector. exit by means of one of the internal interrupt sources results in the mcu taking the appropriate interrupt vector. 3.6.3 active bdm enabled in stop mode entry into the active background mode from run mode is enabled if the enbdm bit in bdcscr is set. this register is described in chapter 12, ?evelopment support of this data sheet. if enbdm is set when the cpu executes a stop instruction, the system clocks to the background debug logic remain active when the mcu enters stop mode so background debug communication is still possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. if the user attempts to enter stop2 with enbdm set, the mcu will instead enter stop3. most background commands are not available in stop mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. after entering background debug mode, all background commands are available. table 3-2 summarizes the behavior of the mcu in stop when entry into the background debug mode is enabled. 4 datasheet u .com chapter 3 modes of operation MC9S08QD4 data sheet, rev. 1 freescale semiconductor 31 3.6.4 lvd enabled in stop mode the lvd system is capable of generating either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enabled in stop by setting the lvde and the lvdse bits, then the voltage regulator remains active during stop mode. if the user attempts to enter stop2 with the lvd enabled for stop, the mcu will instead enter stop3. table 3-3 summarizes the behavior of the mcu in stop when the lvd is enabled. 3.6.5 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal peripheral modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. refer to 3.6.1, ?top2 mode , and 3.6.2, ?top3 mode , for speci? information on system behavior in stop modes. table 3-2. bdm enabled stop mode behavior mode ppdc cpu, digital peripherals, flash ram ics adc1 regulator i/o pins rti stop3 0 standby standby active optionally on active states held optionally on table 3-3. lvd enabled stop mode behavior mode ppdc cpu, digital peripherals, flash ram ics adc1 regulator i/o pins rti stop3 0 standby standby off 1 1 ics can be con?ured to run in stop3. please see the ics registers. optionally on active states held optionally on table 3-4. stop mode behavior peripheral mode stop2 stop3 cpu off standby ram standby standby flash off standby parallel port registers off standby adc1 off optionally on 1 1 requires the asynchronous adc clock and lvd to be enabled, else in standby. ics off standby tpm1 & tpm2 off standby voltage regulator standby standby i/o pins states held states held 4 datasheet u .com chapter 3 modes of operation MC9S08QD4 data sheet, rev. 1 32 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 33 chapter 4 memory map and register de?ition 4.1 MC9S08QD4 memory map as shown in figure 4-1 , on-chip memory in the MC9S08QD4 mcu consists of ram, flash program memory for non-volatile data storage, and i/o and control/status registers. the registers are divided into these groups: direct-page registers (0x0000 through 0x005f) high-page registers (0x1800 through 0x184f) non-volatile registers (0xffb0 through 0xffbf) figure 4-1. MC9S08QD4 memory map direct page registers ram high page registers 256 bytes 0x0000 0x005f 0x0060 0x1800 0x17ff 0x184f 0xffff flash 4,096 bytes 0x1850 0x015f 0x0160 unimplemented 5,792 bytes unimplemented 55,216 bytes 0xf000 0xefff 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 34 freescale semiconductor 4.2 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. the vector names shown in this table are the labels used in the freescale semiconductor-provided equate file for the MC9S08QD4. table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:ffc1 0xffce:ffcf unused vector space (available for user program) 0xffd0:ffd1 rti vrti 0xffd2:ffd3 reserved 0xffd4:ffd5 reserved 0xffd6:ffd7 reserved 0xffd8:ffd9 adc1 conversion vadc1 0xffda:ffdb kbi interrupt vkeyboard1 0xffdc:ffdd reserved 0xffde:ffdf reserved 0xffe0:ffe1 reserved 0xffe2:ffe3 reserved 0xffe4:ffe5 reserved 0xffe6:ffe7 reserved 0xffe8:ffe9 reserved 0xffea:ffeb tpm2 over?w vtpm2ovf 0xffec:ffed reserved 0xffee:ffef tpm2 channel 0 vtpm2ch0 0xfff0:fff1 tpm1 over?w vtpm1ovf 0xfff2:fff3 tpm1 channel 1 vtpm1ch1 0xfff4:fff5 tpm1 channel 0 vtpm1ch0 0xfff6:fff7 reserved 0xfff8:fff9 irq irq 0xfffa:fffb low voltage detect vlvd 0xfffc:fffd swi vswi 0xfffe:ffff reset vreset 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 35 4.3 register addresses and bit assignments the registers in the MC9S08QD4 are divided into these groups: direct-page registers are located in the ?st 96 locations in the memory map; these are accessible with ef?ient direct addressing mode instructions. high-page registers are used much less often, so they are located above 0x1800 in the memory map. this leaves more room in the direct page for more frequently used registers and ram. the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?xffbf. nonvolatile register locations include: nvprot and nvopt are loaded into working registers at reset an 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with ef?ient direct addressing mode instructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page registers and control bits. the direct page registers in table 4-2 can use the more ef?ient direct addressing mode that requires only the lower byte of the address. because of this, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-4 , the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. table 4-2. direct-page register summary address register name bit 7 654321 bit 0 0x00 00 ptad 0 0 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 0x00 01 ptadd 0 0 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 0x00 02 0x00 0b reserved 0x00 0c kbisc 0 0 0 0 kbf kback kbie kbimod 0x00 0d kbipe kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 0x00 0e kbies kbedg7 kbedg6 kbedg5 kbedg4 kbedg3 kbedg2 kbedg1 kbedg0 0x00 0f irqsc 0 irqpdd irqedg irqpe irqf irqack irqie irqmod 0x00 10 adcsc1 coco aien adco adch 0x00 11 adcsc2 adact adtrg acfe acfgt 0x00 12 adcrh 0 0 0 0 0 0 adr9 adr8 0x00 13 adcrl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adccvh 0 0 0 0 0 0 adcv9 adcv8 0x00 15 adccvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adccfg adlpc adiv adlsmp mode adiclk 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 36 freescale semiconductor high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. 0x00 17 apctl1 adpc3 adpc2 adpc1 adpc0 0x00 18 reserved 0x00 19 reserved 0x00 1a 0x00 1f reserved 0x00 20 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm2cntl bit 7 654321 bit 0 0x00 23 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm2modl bit 7 654321 bit 0 0x00 25 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm2c0vl bit 7 654321 bit 0 0x00 28 0x00 37 reserved 0x00 38 icsc1 0 clks 0 0 0 1 1 irefsten 0x00 39 icsc2 bdiv 0 0lp 0 0 0 0x00 3a icstrm trim 0x00 3b icssc 0 0 0 0 0 clkst 0 ftrim 0x00 3c reserved 0x00 40 tpmsc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 41 tpmcnth bit 15 14 13 12 11 10 9 bit 8 0x00 42 tpmcntl bit 7 654321 bit 0 0x00 43 tpmmodh bit 15 14 13 12 11 10 9 bit 8 0x00 44 tpmmodl bit 7 654321 bit 0 0x00 45 tpmc0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 46 tpmc0vh bit 15 14 13 12 11 10 9 bit 8 0x00 47 tpmc0vl bit 7 654321 bit 0 0x00 48 tpmc1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 49 tpmc1vh bit 15 14 13 12 11 10 9 bit 8 0x00 4a tpmc1vl bit 7 654321 bit 0 0x00 4b 0x00 5f reserved table 4-2. direct-page register summary (continued) address register name bit 7 654321 bit 0 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 37 nonvolatile flash registers, shown in table 4-4 , are located in the flash memory. these registers include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt working registers in the high-page registers to control security and block protection options. table 4-3. high-page register summary address register name bit 7 654321 bit 0 0x1800 srs por pin cop ilop ilad 0 lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0 bdfr 0x1802 sopt1 cope copt stope 0 0 0 bkgdpe rstpe 0x1803 sopt2 copclks 0 0 0 0 0 0 0 0x 1804 reserved 0x1805 reserved 0x1806 sdidh rev3 rev2 rev1 rev0 id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 srtisc rtif rtiack rticlks rtie 0 rtis 0x1809 spmsc1 lvdf lvdack lvdie lvdre lvdse lvde 0 1 1 this reserved bit must always be written to 0. bgbe 0x180a spmsc2 lvwf lvwack lvdv lvwv ppdf ppdack ppdc 0x180b 0x181f reserved 0x1820 fcdiv divld prdiv8 div 0x1821 fopt keyen fnored 0 0 0 0 sec01 sec00 0x1822 reserved 0x1823 fcnfg 0 0 keyacc 0 0 0 0 0 0x1824 fprot fps fpdis 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd 0x1827 0x183f reserved 0x1840 ptape 0 0 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 0x1841 ptase 0 0 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 0x1842 ptads 0 0 ptads5 ptads4 ptads3 ptads2 ptads1 ptads0 0x1843 0x1847 reserved 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 38 freescale semiconductor provided the key enable (keyen) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. this key mechanism can be accessed only through user code running in secure memory. (a security key cannot be entered directly through background debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. to avoid returning to secure mode after the next reset, program the security bits (sec01:sec00) to the unsecured state (1:0). the ics factory-trimmed value will be stored in 0xffae (bit-0) and 0xffaf. development tools, such as programmers can trim the ics and the internal temperature sensor (via the adc) and store the values in 0xffad?xffaf. 4.4 ram the MC9S08QD4 includes static ram. the locations in ram below 0x0100 can be accessed using the more ef?ient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or stop3 mode. at power-on or after wakeup from stop1, the contents of ram are uninitialized. ram data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for ram retention (v ram ). table 4-4. nonvolatile register summary address register name bit 7 654321 bit 0 0xffaa 0xffac reserved 0xffad reserved for adcrl of ad26 value during ics trim adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0xffae reserved for adcrh of ad26 value during ics trim and ics trim value ?trim adr9 adr8 ftrim 0xffaf reserved for ics trim value ?rim trim 0xffb0 0xffb7 nvbackkey 8-byte comparison key 0xffb8 0xffbc reserved 0xffbd nvprot fps fpdis 0xffbe unused 0xffbf nvopt keyen fnored 0 0 0 0 sec01 sec00 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 39 for compatibility with m68hc05 mcus, the hcs08 resets the stack pointer to 0x00ff. in the MC9S08QD4, it is usually best to reinitialize the stack pointer to the top of the ram so the direct page ram can be used for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is equated to the highest address of the ram in the freescale semiconductor-provided equate ?e). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource and is not accessible through bdm or through code executing from non-secure memory. see 4.6, ?ecurity , for a detailed description of the security feature. 4.5 flash the flash memory is intended primarily for program storage. in-circuit programming allows the operating program to be loaded into the flash memory after ?al assembly of the application product. it is possible to program the entire array through the single-wire background debug interface. because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. for a more detailed discussion of in-circuit and in-application programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor document order number hcs08rmv1/d. 4.5.1 features features of the flash memory include: flash size 4,096 bytes (8 pages of 512 bytes each) single power supply program and erase command interface for fast program and erase operation up to 100,000 program/erase cycles at typical voltage and temperature flexible block protection security feature for flash and ram auto power-down for low-frequency read accesses 4.5.2 program and erase times before any program or erase command can be accepted, the flash clock divider register (fcdiv) must be written to set the internal clock for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see 4.7.1, ?lash clock divider register (fcdiv) ?. this register can be written only once, so normally this write is performed during reset initialization. fcdiv cannot be written if the access error ?g, faccerr in fstat, is set. the user must ensure that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of these timing pulses is used by the command processor to complete a program or erase command. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 40 freescale semiconductor table 4-5 shows program and erase times. the bus clock frequency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk = 1/f fclk . the times are shown as a number of cycles of fclk and as an absolute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. 4.5.3 program and erase command execution the steps for executing any of the commands are listed below. the fcdiv register must be initialized and any error ?gs cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash array. the address and data information from this write is latched into the flash interface. this write is a required ?st step in any command sequence. for erase and blank check commands, the value of the data is not important. for page erase commands, the address can be any address in the 512-byte page of flash to be erased. for mass erase and blank check commands, the address can be any address in the flash memory. whole pages of 512 bytes are the smallest block of flash that can be erased. note a mass or page erase of the last page in flash will erase the factory programmed internal reference clock trim value. do not program any byte in the flash more than once after a successful erase operation. reprogramming bits in a byte which is already programmed is not allowed without ?st erasing the page in which the byte resides or mass erasing the entire flash memory. programming without ?st erasing may disturb data stored in the flash. 2. write the command code for the desired command to fcmd. the ve valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr access error ?g which must be cleared before starting a new command. table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s 1 1 excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 41 a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended changes to the flash memory contents. the command complete ?g (fccf) indicates when a command is complete. the command sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a ?wchart for executing all of the commands except for burst programming. the fcdiv register must be initialized following any reset before using any flash commands. figure 4-2. flash program and erase flowchart 4.5.4 burst program execution the burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. this is possible because the high voltage to the flash array does not need to be disabled between program operations. ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the command, the charge pump is turned off. when a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met: start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) required only once after reset. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 42 freescale semiconductor the next burst program command has been queued before the current program operation has completed. the next sequential address selects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins when addresses a5 through a0 are all 0s. the ?st byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. subsequent bytes will program in the burst program time provided that the conditions above are met. in the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. figure 4-3. flash burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) no yes new burst command ? 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 1 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) required only once after reset. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 43 4.5.5 access errors an access error occurs whenever the command execution protocol is violated. any of the following speci? actions will cause the access error ?g (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. writing to a flash address before the internal flash clock frequency has been set by writing to the fcdiv register writing to a flash address while fcbef is not set (a new command cannot be started until the command buffer is empty.) writing a second time to a flash address before launching the previous command (there is only one write to flash for every command.) writing a second time to fcmd before launching the previous command (there is only one write to fcmd for every command.) writing to any flash control register other than fcmd after writing to a flash address writing any command code other than the ve allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to fcmd accessing (read or write) any flash control register other than to write to fstat (to clear fcbef and launch the command) after writing the command to fcmd. the mcu enters stop mode while a program or erase command is in progress (the command is aborted.) writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a background debug command while the mcu is secured (the background debug controller can do blank check and mass erase commands only when the mcu is secure.) writing 0 to fcbef to cancel a partial command 4.5.6 flash block protection the block protection feature prevents the protected region of flash from program or erase changes. block protection is controlled through the flash protection register (fprot). when enabled, block protection begins at any 512 byte boundary below the last address of flash, 0xffff. (see 4.7.4, ?lash protection register (fprot and nvprot) ?. after exit from reset, fprot is loaded with the contents of the nvprot location which is in the nonvolatile register block of the flash memory. fprot cannot be changed directly from application software so a runaway program cannot alter the block protection settings. because nvprot is within the last 512 bytes of flash, if any amount of memory is protected, nvprot is itself protected and cannot be altered (intentionally or unintentionally) by the application software. fprot can be written through background debug commands, which allows a way to erase and reprogram a protected flash memory. the block protection mechanism is illustrated in figure 4-4 . the fps bits are used as the upper bits of the last address of unprotected memory. this address is formed by concatenating fps7:fps1 with logic 1 bits as shown. for example, in order to protect the last 8192 bytes of memory (addresses 0xe000 through 0xffff), the fps bits must be set to 1101 111, which results in the value 0xdfff as the last address of unprotected memory. in addition to programming the fps bits to the appropriate value, fpdis (bit 0 of 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 44 freescale semiconductor nvprot) must be programmed to logic 0 to enable block protection. therefore the value 0xde must be programmed into nvprot to protect addresses 0xe000 through 0xffff. figure 4-4. block protection mechanism one use for block protection is to block protect an area of flash memory for a bootloader program. this bootloader program then can be used to erase the rest of the flash memory and reprogram it. because the bootloader is protected, it remains intact even if mcu power is lost in the middle of an erase and reprogram operation. 4.5.7 vector redirection whenever any block protection is enabled, the reset and interrupt vectors will be protected. vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to 0. for redirection to occur, at least some portion but not all of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all of the interrupt vectors (memory locations 0xffc0?xfffd) are redirected, though the reset vector (0xfffe:ffff) is not. for example, if 512 bytes of flash are protected, the protected address region is from 0xfe00 through 0xffff. the interrupt vectors (0xffc0?xfffd) are redirected to the locations 0xfdc0?xfdfd. for example, vector redirection is enabled and an interrupt occurs, the values in the locations 0xfde0:fde1 are used for the vector instead of the values in the locations 0xffe0:ffe1. this allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.6 security the MC9S08QD4 includes circuitry to prevent unauthorized access to the contents of flash and ram memory. when security is engaged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the state of two register bits (sec01:sec00) in the fopt register. during reset, the contents of the nonvolatile location nvopt are copied from flash into the working fopt register in high-page register space. a user engages security by programming the nvopt location, which can be performed at the same time the flash memory is programmed. the 1:0 state disengages security and the other three combinations engage security. notice the erased state (1:1) makes fps7 fps6 fps5 fps4 fps3 fps2 fps1 a15 a14 a13 a12 a11 a10 a9 a8 1 a7 a6 a5 a4 a3 a2 a1 a0 111 11111 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 45 the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec00 bit to 0 in nvopt so sec01:sec00 = 1:0. this would allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd/ms low at the rising edge of reset. a user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile keyen bit in nvopt/fopt is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporarily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbackkey+7) as values to be compared against the key rather than as the ?st step in a flash program or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be performed in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx must not be used for these writes because these writes cannot be performed on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication interface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was written matches the key stored in the flash locations, sec01:sec00 are automatically changed to 1:0 and security will be disengaged until the next reset. the security key can be written only from secure memory (either ram or flash), so it cannot be entered through background commands without the cooperation of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other flash memory location. the nonvolatile registers are in the same 512-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through the background debug interface by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 46 freescale semiconductor 4.7 flash registers and control bits the flash module has nine 8-bit registers in the high-page register space, two locations (nvopt, nvprot) in the nonvolatile register space in flash memory are copied into corresponding high-page control registers (fopt, fprot) at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all flash registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses. 4.7.1 flash clock divider register (fcdiv) before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. if prdiv8 = 0 ?f fclk = f bus (div + 1) eqn. 4-1 if prdiv8 = 1 ?f fclk = f bus (8 (div + 1)) eqn. 4-2 table 4-7 shows the appropriate values for prdiv8 and div for selected bus frequencies. 76543210 r divld prdiv8 div w reset 00000000 = unimplemented or reserved figure 4-5. flash clock divider register (fcdiv) table 4-6. fcdiv register field descriptions field description 7 divld divisor loaded status flag when set, this read-only status ?g indicates that the fcdiv register has been written since reset. reset clears this bit and the ?st write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash. 1 fcdiv has been written since reset; erase and program operations enabled for flash. 6 prdiv8 prescale (divide) flash clock by 8 0 clock input to the flash clock divider is the bus rate clock. 1 clock input to the flash clock divider is the bus rate clock divided by 8. 5:0 div divisor for flash clock divider the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div ?ld plus one. the resulting frequency of the internal flash clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this internal flash clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 and equation 4-2 . 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 47 4.7.2 flash options register (fopt and nvopt) during reset, the contents of the nonvolatile location nvopt are copied from flash into fopt. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. table 4-7. flash clock divider settings f bus prdiv8 (binary) div (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s 76543210 r keyen fnored 0000 sec01 sec00 w reset this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-6. flash options register (fopt) table 4-8. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ?when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) ?mware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to 4.6, ?ecurity . 0 no backdoor key access allowed. 1 if user ?mware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is temporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ?when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 1:0 sec0[1:0] security state code this 2-bit ?ld determines the security state of the mcu as shown in table 4-9 . when the mcu is secure, the contents of ram and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. for more detailed information about security, refer to 4.6, ?ecurity . 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 48 freescale semiconductor 4.7.3 flash con?uration register (fcnfg) 4.7.4 flash protection register (fprot and nvprot) during reset, the contents of the nonvolatile location nvprot is copied from flash into fprot. this register can be read at any time, but user program writes have no meaning or effect. figure 4-8. flash protection register (fprot) table 4-9. security states 1 1 sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. sec01:sec00 description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 76543210 r0 0 keyacc 00000 w reset 00000000 = unimplemented or reserved figure 4-7. flash con?uration register (fcnfg) table 4-10. fcnfg register field descriptions field description 5 keyacc enable writing of access key ?this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to 4.6, ?ecurity . 0 writes to 0xffb0?xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?xffb7) are interpreted as comparison key writes. 76543210 r fps (1) 1 background commands can be used to change the contents of these bits in fprot. fpdis (1) w reset this register is loaded from nonvolatile location nvprot during reset. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 freescale semiconductor 49 4.7.5 flash status register (fstat) table 4-11. fprot register field descriptions field description 7:1 fps flash protect select bits when fpdis = 0, this 7-bit ?ld determines the ending address of unprotected flash locations at the high address end of the flash. protected flash locations cannot be erased or programmed. 0 fpdis flash protection disable 0 flash block speci?d by fps7:fps1 is block protected (program and erase not allowed). 1 no flash block is protected. 76543210 r fcbef fccf fpviol faccerr 0 fblank 0 0 w reset 11000000 = unimplemented or reserved figure 4-9. flash status register (fstat) table 4-12. fstat register field descriptions field description 7 fcbef flash command buffer empty flag the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command can be written to the command buffer. 6 fccf flash command complete flag ?fccf is set automatically when the command buffer is empty and no command is being processed. fccf is cleared automatically when a new command is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag ?fpviol is set automatically when fcbef is cleared to register a command that attempts to erase or program a location in a protected block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location. 4 datasheet u .com chapter 4 memory map and register de?ition MC9S08QD4 data sheet, rev. 1 50 freescale semiconductor 4.7.6 flash command register (fcmd) only ve command codes are recognized in normal user modes as shown in table 4-13 . refer to 4.5.3, ?rogram and erase command execution , for a detailed discussion of flash programming and erase operations. all other command codes are illegal and generate an access error. it is not necessary to perform a blank check command after a mass erase operation. only blank check is required as part of the security unlocking mechanism. 4 faccerr access error flag faccerr is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the fcdiv register has been initialized, or if the mcu enters stop while a command was in progress. for a more detailed discussion of the exact actions that are considered access errors, see 4.5.5, ?ccess errors . faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank flash veri?d as all blank (erased) flag fblank is set automatically at the conclusion of a blank check command if the entire flash array was veri?d to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all 0xff). 76543210 r00000000 w fcmd reset 00000000 = unimplemented or reserved figure 4-10. flash command register (fcmd) table 4-13. flash commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog byte program ?burst mode 0x25 mburstprog page erase (512 bytes/page) 0x40 mpageerase mass erase (all flash) 0x41 mmasserase table 4-12. fstat register field descriptions (continued) field description 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 51 chapter 5 resets, interrupts, and general system control 5.1 introduction this section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08QD4. some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. this section gathers basic information about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog and real-time interrupt (rti), are not part of on-chip peripheral systems with their own chapters but are part of the system control logic. 5.2 features reset and interrupt features include: multiple sources of reset for ?xible system con?uration and reliable operation reset status register (srs) to indicate source of most recent reset separate interrupt vectors for each module (reduces polling overhead) (see table 5-2 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral modules are disabled and i/o pins are initially con?ured as general-purpose high-impedance inputs with pullup devices disabled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system control settings. sp is forced to 0x00ff at reset. the MC9S08QD4 has the following sources for reset: external pin reset (pin) - enabled using rstpe in sopt1 power-on reset (por) low-voltage detect (lvd) computer operating properly (cop) timer illegal opcode detect (ilop) illegal address detect (ilad) background debug forced reset each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 52 freescale semiconductor 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset when the application software fails to execute as expected. to prevent a system reset from the cop timer (when it is enabled), application software must reset the cop counter periodically. if the application program gets lost and fails to reset the cop counter before it times out, a system reset is generated to force the system back to a known starting point. after any reset, the cope becomes set in sopt1 enabling the cop watchdog (see 5.8.5, ?ystem options register 2 (sopt2) , for additional information). if the cop watchdog is not used in an application, it can be disabled by clearing cope. the cop counter is reset by writing any value to the address of srs. this write does not affect the data in the read-only srs. instead, the act of writing to this address is decoded and sends a reset signal to the cop counter. the copclks bit in sopt2 (see 5.8.5, ?ystem options register 2 (sopt2) , for additional information) selects the clock source used for the cop timer. the clock source options are either the bus clock or an internal 32-khz clock source. with each clock source, there is an associated short and long time-out controlled by copt in sopt1. table 5-1 summaries the control functions of the copclks and copt bits. the cop watchdog defaults to operation from the 32-khz clock source and the associated long time-out (2 8 cycles). even if the application will use the reset default settings of cope, copclks and copt, the user must write to the write-once sopt1 and sopt2 registers during reset initialization to lock in the settings. that way, they cannot be changed accidentally if the application program gets lost. the initial writes to sopt1 and sopt2 will reset the cop counter. the write to srs that services (clears) the cop counter must not be placed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. in background debug mode, the cop counter will not increment. when the bus clock source is selected, the cop counter does not increment while the system is in stop mode. the cop counter resumes once the mcu exits stop mode. when the 32-khz clock source is selected, the cop counter is re-initialized to zero upon entry to stop mode. the cop counter begins from zero once the mcu exits stop mode. table 5-1. cop con?uration options control bits clock source cop over?w count copclks copt 00 ~32 khz 2 10 cycles (32 ms) 1 1 values are shown in this column based on t rti = 1 ms. see t rti in the appendix a.8.1, ?ontrol timing , for the tolerance of this value. 01 ~32 khz 2 13 cycles (256 ms) 1 10 bus 2 13 cycles 11 bus 2 18 cycles 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 53 5.5 interrupts interrupts provide a way to save the current cpu status and registers, execute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it was before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caused by hardware events such as an edge on the irq pin or a timer-over?w event. the debug module can also generate an swi under certain circumstances. if an event occurs in an enabled interrupt source, an associated read-only status ?g will become set. the cpu will not respond until and unless the local interrupt enable is a 1 to enable the interrupt. the i bit in the ccr is 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which masks (prevents) all maskable interrupt sources. the user program initializes the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a quali?d interrupt request, it completes the current instruction before responding to the interrupt. the interrupt sequence obeys the same cycle-by-cycle sequence as the swi instruction and consists of: saving the cpu registers on the stack setting the i bit in the ccr to mask further interrupts fetching the interrupt vector for the highest-priority interrupt that is currently pending filling the instruction queue with the ?st three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restored from the value stacked on entry to the isr. in rare cases, the i bit can be cleared inside an isr (after clearing the status ?g that generated the interrupt) so that other interrupts can be serviced without waiting for the ?st service routine to ?ish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are dif?ult to debug. the interrupt service routine ends with a return-from-interrupt (rti) instruction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information off the stack. note for compatibility with m68hc08 devices, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service routine (isr) and restore it immediately before the rti that is used to return from the isr. when two or more interrupts are pending when the i bit is cleared, the highest priority source is serviced ?st (see table 5-2 ). 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 54 freescale semiconductor 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next available byte location on the stack. the current values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next available location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu ?ls the instruction pipeline by reading three bytes of program information, starting from the pc address recovered from the stack. the status ?g causing the interrupt must be acknowledged (cleared) before returning from the isr. typically, the ?g is cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irq status and control register, irqsc. when the irq function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 pin con?uration options the irq pin enable (irqpe) control bit in irqsc must be 1 in order for the irq pin to act as the interrupt request (irq) input. as an irq input, the user can choose the polarity of edges or levels detected (irqedg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or only sets the irqf ?g which can be polled by software. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index register is not automatically stacked. * program counter low 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 55 the irq pin when enabled defaults to use an internal pull device (irqpdd = 0), the device is a pullup or pulldown depending on the polarity to detect. if the user desires to use an external pullup or pulldown, the irqpdd can be written to a 1 to turn off the internal device. bih and bil instructions may be used to detect the level on the irq pin when the pin is con?ured to act as the irq input. note this pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up irq pin may be as low as v dd 0.7 v. the internal gates connected to this pin are pulled all the way to v dd . 5.5.2.2 edge and level sensitivity the irqmod control bit recon?ures the detection logic so it detects edge events and pin levels. in this edge detection mode, the irqf status ?g becomes set when an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the ?g is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-2 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byte of the address for the interrupt service routine is located at the ?st address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated ?g bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will ?ish the current instruction; stack the pcl, pch, x, a, and ccr cpu registers; set the i bit; and then fetch the interrupt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 56 freescale semiconductor 5.6 low-voltage detect (lvd) system the MC9S08QD4 includes a system to protect against low voltage conditions in order to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and an lvd circuit with a user selectable trip voltage, either high (v lvdh ) or low (v lvdl ). the lvd circuit is enabled when lvde in spmsc1 is high and the trip voltage is selected by lvdv in spmsc3. the lvd is disabled upon entering any of the stop modes unless lvdse is set in spmsc1. if lvdse and lvde are both set, then the mcu cannot enter stop1 or stop2, and the current consumption in stop3 with the lvd enabled will be greater. table 5-2. vector summary vector priority vector number address (high:low) vector name module source enable description lower higher 31 through 24 0xffc0:ffc1 through 0xffce:ffcf unused vector space (available for user program) 23 0xffd0:ffd1 vrti system control rtif rtie real-time interrupt 22 0xffd2:ffd3 21 0xffd4:ffd5 20 0xffd6:ffd7 19 0xffd8:ffd9 vadc1 adc1 coco aien adc1 18 0xffda:ffdb vkeyboard1 kbi1 kbf kbie keyboard pins 17 0xffdc:ffdd 16 0xffde:ffdf 15 0xffe0:ffe1 14 0xffe2:ffe3 13 0xffe4:ffe5 12 0xffe6:ffe7 11 0xffe8:ffe9 10 0xffea:ffeb vtpm2ovf tpm2 tof toie tpm2 over?w 9 0xffec:ffed 8 0xffee:ffef vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 7 0xfff0:fff1 vtpm1ovf tpm1 tof toie tpm1 over?w 6 0xfff2:fff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4:fff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6:fff7 3 0xfff8:fff9 virq irq irrqf irqie irq pin 2 0xfffa:fffb vlvd system control lvdf lvdie low voltage detect 1 0xfffc:fffd vswi cpu swi instruction software interrupt 0 0xfffe:ffff vreset system control cop lv d reset pin illegal opcode illegal address por cope lvdre rstpe watchdog timer low-voltage detect external pin illegal opcode illegal address power-on-reset 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 57 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the v por level, the por circuit will cause a reset condition. as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above the v lvdl level. both the por bit and the lvd bit in srs are set following a por. 5.6.2 lvd reset operation the lvd can be con?ured to generate a reset upon detection of a low voltage condition by setting lvdre to 1. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the level determined by lvdv. the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 lvd interrupt operation when a low voltage condition is detected and the lvd circuit is con?ured using spmsc1 for interrupt operation (lvde set, lvdie set, and lvdre clear), then lvdf in spmsc1 will be set and an lvd interrupt request will occur. 5.6.4 low-voltage warning (lvw) the lvd system has a low voltage warning ?g to indicate to the user that the supply voltage is approaching, but is above, the lvd voltage. the lvw does not have an interrupt associated with it. there are two user selectable trip voltages for the lvw, one high (v lvwh ) and one low (v lvwl ). the trip voltage is selected by lvwv in spmsc3. 5.7 real-time interrupt (rti) the real-time interrupt function can be used to generate periodic interrupts. the rti can accept two sources of clocks, the 1-khz internal clock or an 32-khz ics clock if available. the rticlks bit in srtisc is used to select the rti clock source. both clock source can be used when the mcu is in run, wait or stop3 mode. when using the 32-khz ics clock in stop3, it must be enabled in stop (erefsten = 1) and con?ured for low frequency operation (range = 0). only the internal 1-khz clock source can be selected to wake the mcu from stop1 or stop2 modes. the srtisc register includes a read-only status ?g, a write-only acknowledge bit, and a 3-bit control value (rtis) used to select one of seven wakeup periods. the rti has a local interrupt enable, rtie, to allow masking of the real-time interrupt. the rti can be disabled by writing each bit of rtis to zeroes, and no interrupts will be generated. see 5.8.7, ?ystem real-time interrupt status and control register (srtisc) , for detailed information about this register. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 58 freescale semiconductor 5.8 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. refer to the direct-page register summary in chapter 3, ?odes of operation , for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. some control bits in the sopt1, sopt2 and spmsc2 registers are related to modes of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?odes of operation . 5.8.1 interrupt pin request status and control register (irqsc) this direct page register includes status and control bits which are used to con?ure the irq function, report status, and acknowledge irq events. 76543210 r0 irqpdd irqedg irqpe irqf 0 irqie irqmod w irqack reset 00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc) table 5-3. irqsc register field descriptions field description 6 irqpdd interrupt request (irq) pull device disable ?this read/write control bit is used to disable the internal pullup/pulldown device when the irq pin is enabled (irqpe = 1) allowing for an external device to be used. 0 irq pull device enabled if irqpe = 1. 1 irq pull device disabled if irqpe = 1. 5 irqedg interrupt request (irq) edge select ?this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the irq pin is enabled as the irq input and is con?ured to detect rising edges. when irqedg = 1 and the internal pull device is enabled, the pullup device is recon?ured as an optional pulldown device. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable this read/write control bit enables the irq pin function. when this bit is set the irq pin can be used as an interrupt request. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ?this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 59 5.8.2 system reset status register (srs) this high-page register includes read-only status ?gs to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdfr register, all of the status bits in srs will be cleared. writing any value to this register address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset. figure 5-3. system reset status (srs) 2 irqack irq acknowledge this write-only bit is used to acknowledge interrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detection is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ?this read/write control bit determines whether irq events generate an interrupt request. 0 interrupt request when irqf set is disabled (use polling). 1 interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ?this read/write control bit selects either edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see 5.5.2.2, ?dge and level sensitivity ?for more details. 0 irq event on falling edges or rising edges only. 1 irq event on falling edges and low levels or on rising edges and high levels. 76543210 r por pin cop ilop ilad 0 lvd 0 w writing any value to srs address clears cop watchdog timer. por: 10000010 lvr: 00000010 any other reset: 0 (1) 1 any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. (1) (1) (1) 000 table 5-4. srs register field descriptions field description 7 por power-on reset reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvr) status bit is also set to indicate that the reset occurred while the internal supply was below the lvr threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ?reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. table 5-3. irqsc register field descriptions (continued) field description 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 60 freescale semiconductor 5.8.3 system background debug force reset register (sbdfr) this high-page register contains a single write-only control bit. a serial background command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. figure 5-4. system background debug force reset register (sbdfr) 5 cop computer operating properly (cop) watchdog reset was caused by the cop watchdog timer timing out. this reset source can be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode reset was caused by an attempt to execute an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt register. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode. 3 ilad illegal address reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 reset not caused by an illegal address 1 reset caused by an illegal address 1 lv d low voltage detect if the lvdre bit is set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background debug commands, not from user programs. reset: 00000000 = unimplemented or reserved table 5-5. sbdfr register field descriptions field description 0 bdfr background debug force reset a serial background command such as write_byte can be used to allow an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program. to enter user mode, pta4/tpm2ch0o/bkgd/ms must be high immediately after issuing write_byte command. to enter bdm, pta4/tpm2ch0o/bkgd/ms must be low immediately after issuing write_byte command. see a.8.1, ?ontrol timing ?for more information. table 5-4. srs register field descriptions (continued) field description 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 61 5.8.4 system options register 1 (sopt1) this high-page register is a write-once register so only the ?st write after reset is honored. it can be read at any time. any subsequent attempt to write to sopt1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt1 must be written during the user s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7654 1 1 bit 4 is reserved, writes will change the value but will have no effect on this mcu. 3210 r cope copt stope 00 bkgdpe rstpe w reset: 1101001u 2 2 u = unaffected por: 11010010 = unimplemented or reserved figure 5-5. system options register 1 (sopt1) table 5-6. sopt1 register field descriptions field description 7 cope cop watchdog enable ?this write-once bit selects whether the cop watchdog is enabled. 0 cop watchdog timer disabled. 1 cop watchdog timer enabled (force reset on timeout). 6 copt cop watchdog timeout ?this write-once bit selects the timeout period of the cop. copt along with copclks in sopt2 de?es the cop timeout period. 0 short timeout period selected. 1 long timeout period selected. 5 stope stop mode enable ?this write-once bit is used to enable stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled. 1 bkgdpe background debug mode pin enable ?this write-once bit when set enables the pta4/tpm2ch0o/bkgd/ms pin to function as bkgd/ms. when clear, the pin functions as one of its output only alternative functions. this pin defaults to the bkgd/ms function following any mcu reset. 0 pta4/tpm2ch0o/bkgd/ms pin functions as pta4 or tpm2ch0o. 1 pta4/tpm2ch0o/bkgd/ms pin functions as bkgd/ms. 0 rstpe reset pin enable this write-once bit when set enables the pta5/tpm2ch0i/irq/ reset pin to function as reset. when clear, the pin functions as one of its input only alternative functions. this pin defaults to its input-only port function following an mcu por. when rstpe is set, an internal pullup device is enabled on reset. 0 pta5/tpm2ch0i/irq/ reset pin functions as pta5, irq or tpm2ch0i. 1 pta5/tpm2ch0i/irq/ reset pin functions as reset. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 62 freescale semiconductor 5.8.5 system options register 2 (sopt2) this high-page register contains bits to con?ure mcu speci? features on the MC9S08QD4 devices. 5.8.6 system device identi?ation register (sdidh, sdidl) these high-page read-only registers are included so host development systems can identify the hcs08 derivative and revision number. this allows the development software to recognize where speci? memory blocks, registers, and control bits are located in a target mcu. figure 5-7. system device identi?ation register ?high (sdidh) 76543210 r copclks 1 1 this bit can be written only one time after reset. additional writes are ignored. 0000000 w reset: 00000000 = unimplemented or reserved figure 5-6. system options register 2 (sopt2) table 5-7. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ?this write-once bit selects the clock source of the cop watchdog. 0 internal 32-khz clock is source to cop. 1 bus clock is source to cop. 76543210 r rev3 rev2 rev1 rev0 id11 id10 id9 id8 w reset: 0 1 1 the revision number that is hard coded into these bits re?cts the current silicon revision level. 0 1 0 1 0 1 0000 = unimplemented or reserved table 5-8. sdidh register field descriptions field description 7:4 rev[3:0] revision number ?the high-order 4 bits of address sdidh are hard coded to re?ct the current mask set revision number (0?). 3:0 id[11:8] part identi?ation number ?each derivative in the hcs08 family has a unique identi?ation number. the MC9S08QD4 is hard coded to the value 0x011. see also id bits in table 5-9 . 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 63 5.8.7 system real-time interrupt status and control register (srtisc) this high-page register contains status and control bits for the rti. 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w reset: 00001001 = unimplemented or reserved figure 5-8. system device identi?ation register ?low (sdidl) table 5-9. sdidl register field descriptions field description 7:0 id[7:0] part identi?ation number ?each derivative in the hcs08 family has a unique identi?ation number. the MC9S08QD4 is hard coded to the value 0x011. see also id bits in table 5-8 . 76543210 r rtif 0 rticlks rtie 0 rtis w rtiack reset: 00000000 = unimplemented or reserved figure 5-9. system rti status and control register (srtisc) table 5-10. srtisc register field descriptions field description 7 rtif real-time interrupt flag ?this read-only status bit indicates the periodic wakeup timer has timed out. 0 periodic wakeup timer not timed out. 1 periodic wakeup timer timed out. 6 rtiack real-time interrupt acknowledge ?this write-only bit is used to acknowledge real-time interrupt request (write 1 to clear rtif). writing 0 has no meaning or effect. reads always return 0. 5 rticlks real-time interrupt clock select ?this read/write bit selects the clock source for the real-time interrupt. 0 real-time interrupt request clock source is internal 1-khz oscillator. 1 real-time interrupt request clock source is 32-khz ics clock. 4 rtie real-time interrupt enable ?this read-write bit enables real-time interrupts. 0 real-time interrupts disabled. 1 real-time interrupts enabled. 2:0 rtis real-time interrupt delay selects ?these read/write bits select the period for the rti. see table 5-11 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 64 freescale semiconductor 5.8.8 system power management status and control 1 register (spmsc1) this high-page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the adc module. to con?ure the low voltage detect trip voltage, see table 5-13 for the lvdv bit description in spmsc2. figure 5-10. system power management status and control 1 register (spmsc1) table 5-11. real-time interrupt period rtis2:rtis1:rtis0 using internal 1-khz clock source 12 1 values are shown in this column based on t rti = 1 ms. see t rti in the appendix a.8.1, ?ontrol timing , for the tolerance of this value. 2 the initial rti timeout period will be up to one 1-khz clock period less than the time speci?d. using 32-khz ics clock source period = t ext 3 3 t ext is the period of the 32-khz ics frequency. 0:0:0 disable rti disable rti 0:0:1 8 ms t ext 256 0:1:0 32 ms t ext 1024 0:1:1 64 ms t ext 2048 1:0:0 128 ms t ext 4096 1:0:1 256 ms t ext 8192 1:1:0 512 ms t ext 16384 1:1:1 1.024 s t ext 32768 7654321 1 1 bit 1 is a reserved bit that must always be written to 0. 0 r lvdf 0 lvdie lvdre 2 2 this bit can be written only one time after reset. additional writes are ignored. lvdse lvde 2 0 bgbe w lv dac k reset: 00011100 = unimplemented or reserved table 5-12. spmsc1 register field descriptions field description 7 lvdf low-voltage detect flag ?provided lvde = 1, this read-only status bit indicates a low-voltage detect event. 6 lv dac k low-voltage detect acknowledge ?this write-only bit is used to acknowledge low voltage detection errors (write 1 to clear lvdf). reads always return 0. 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 65 5.8.9 system power management status and control 2 register (spmsc2) this high-page register contains status and control bits to con?ure the stop mode behavior of the mcu. see 3.6, ?top modes ?for more information on stop modes. figure 5-11. system power management status and control 2 register (spmsc2) 5 lvdie low-voltage detect interrupt enable ?this bit enables hardware interrupt requests for lvdf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvdf = 1. 4 lvdre low-voltage detect reset enable ?this write-once bit enables lvdf events to generate a hardware reset (provided lvde = 1). 0 lvdf does not generate hardware resets. 1 force an mcu reset when lvdf = 1. 3 lvdse low-voltage detect stop enable provided lvde = 1, this read/write bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lvde low-voltage detect enable this write-once bit enables low-voltage detect logic and quali?s the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable this bit enables an internal buffer for the bandgap voltage reference for use by the adc module on one of its internal channels. 0 bandgap buffer disabled. 1 bandgap buffer enabled. 76543210 r lvwf 0 lvdv lvwv ppdf 0 ppdc 1 1 this bit can be written only one time after reset. additional writes are ignored. w lv wac k ppdack por: 0 2 2 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w . 0000000 lvdr: 0 2 0uu0000 other reset 0 2 0uu0000 = unimplemented or reserved u = unaffected by reset table 5-12. spmsc1 register field descriptions (continued) field description 4 datasheet u .com chapter 5 resets, interrupts, and general system control MC9S08QD4 data sheet, rev. 1 66 freescale semiconductor table 5-13. spmsc2 register field descriptions field description 7 lvwf low-voltage warning flag ?the lvwf bit indicates the low voltage warning status. 0 low voltage warning not preset. 1 low voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ?the lvwack bit is the low-voltage warning acknowledge. writing a 1 to lvwack clears lvwf to a 0 if a low voltage warning is not present. 5 lv dv low-voltage detect voltage select ?the lvdv bit selects the lvd trip point voltage (v lv d ). 0 low trip point selected (v lv d = v lvdl ). 1 high trip point selected (v lv d = v lvdh ). 4 lvwv low-voltage warning voltage select ?the lvwv bit selects the lvw trip point voltage (v lv w ). 0 low trip point selected (v lv w = v lvwl ). 1 high trip point selected (v lv w = v lvwh ). 3 ppdf partial power down flag ?the ppdf bit indicates that the mcu has exited the stop2 mode. 0 not stop2 mode recovery. 1 stop2 mode recovery. 2 ppdack partial power down acknowledge ?writing a 1 to ppdack clears the ppdf bit. 0 ppdc partial power down control ?the write-once ppdc bit controls whether stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled. 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 67 chapter 6 parallel input/output control this section explains software controls related to parallel input/output (i/o) and pin control. the MC9S08QD4 has one parallel i/o port which include a total of 4 i/o pins, one output-only pin, and one input-only pin. see chapter 2, ?xternal signal description , for more information about pin assignments and external hardware considerations of these pins. all of these i/o pins are shared with on-chip peripheral functions as shown in table 2-1 . the peripheral modules have priority over the i/os so that when a peripheral is enabled, the i/o functions associated with the shared pins are disabled. after reset, the shared peripheral functions are disabled so that the pins are controlled by the i/o. all of the i/os are con?ured as inputs (ptxddn = 0) with pullup devices disabled (ptxpen = 0), except for output-only pin pta4 which defaults to bkgd/ms pin. note not all general-purpose i/o pins are available on all packages. to avoid extra current drain from ?ating input pins, the user s reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not ?at. 6.1 port data and data direction reading and writing of parallel i/os is performed through the port data registers. the direction, either input or output, is controlled through the port data direction registers. the parallel i/o port function for an individual pin is illustrated in the block diagram shown in figure 6-1 . 4 datasheet u .com chapter 6 parallel input/output control MC9S08QD4 data sheet, rev. 1 68 freescale semiconductor figure 6-1. parallel i/o block diagram the data direction control bit (ptxddn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. the input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin. when a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. however, the data direction register bit will continue to control the source for reads of the port data register. when a shared analog function is enabled for a pin, both the input and output buffers are disabled. a value of 0 is read for any port data bit where the bit is an input (ptxddn = 0) and the input buffer is disabled. in general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. it is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. this ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. 6.2 pin control ?pullup, slew rate and drive strength associated with the parallel i/o ports is a set of registers located in the high-page register space that operate independently of the parallel i/o registers. these registers are used to control pullups, slew rate and drive strength for the pins. q d q d 1 0 port read ptxddn ptxdn output enable output data input data synchronizer data busclk 4 datasheet u .com chapter 6 parallel input/output control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 69 6.3 pin behavior in stop modes pin behavior following execution of a stop instruction depends on the stop mode that is entered. an explanation of pin behavior for the various stop modes follows: in stop1 mode, all internal registers including parallel i/o control and data registers are powered off. each of the pins assumes its default reset state (output buffer and internal pullup disabled). upon exit from stop1, all pins must be re-con?ured the same as if the mcu had been reset. stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the stop instruction was executed. cpu register status and the state of i/o registers must be saved in ram before the stop instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user must examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initialized as if a power on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals previously enabled will require being initialized and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in the spmsc2 register. access of pins is now permitted again in the user s application program. in stop3 mode, all pin states are maintained because internal logic stays powered up. upon recovery, all pin functions are the same as before entering stop3. 6.4 parallel i/o registers 6.4.1 port a registers this section provides information about the registers associated with the parallel i/o ports. refer to tables in chapter 4, ?emory map and register de?ition , for the absolute address assignments for all parallel i/o. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses. 6.4.1.1 port a data (ptad) 76543210 r 00 ptad5 1 1 reads of bit ptad5 always return the pin value of pta5, regardless of the value stored in bit ptadd5. ptad4 2 2 reads of bit ptad4 always return the contents of ptad4, regardless of the value stored in bit ptadd4. ptad3 ptad2 ptad1 ptad0 w reset: 00000000 figure 6-2. port a data register (ptad) 4 datasheet u .com chapter 6 parallel input/output control MC9S08QD4 data sheet, rev. 1 70 freescale semiconductor 6.4.1.2 port a data direction (ptadd) 6.4.2 port a control registers the pins associated with port a are controlled by the registers in this section. these registers control the pin pullup, slew rate and drive strength of the port a pins independent of the parallel i/o register. table 6-1. ptad register field descriptions field description 5:0 ptad[5:0] port a data register bits ?for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port a pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pullups disabled. 76543210 r 00 ptadd5 1 1 ptadd5 has no effect on the input-only pta5 pin. read this bit is always equal to zero. ptadd4 2 2 ptadd4 has no effect on the output-only pta4 pin. ptadd3 ptadd2 ptadd1 ptadd0 w reset: 00000000 figure 6-3. port a data direction register (ptadd) table 6-2. ptadd register field descriptions field description 5:0 ptadd[5:0] data direction for port a bits these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn. 4 datasheet u .com chapter 6 parallel input/output control MC9S08QD4 data sheet, rev. 1 freescale semiconductor 71 6.4.2.1 port a internal pullup enable (ptape) an internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup enable register (ptapen). the pullup device is disabled if the pin is con?ured as an output by the parallel i/o control logic or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. the pullup device is also disabled if the pin is controlled by an analog function. 6.4.2.2 port a slew rate enable (ptase) slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (ptasen). when enabled, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins which are con?ured as inputs. 76543210 r 00 ptape5 ptape4 1 1 ptape4 has no effect on the output-only pta4 pin. ptape3 ptape2 ptape1 ptape0 w reset: 00000000 figure 6-4. internal pullup enable for port a register (ptape) table 6-3. ptape register field descriptions field description 5:0 ptape[5:0] internal pullup enable for port a bits ?each of these control bits determines if the internal pullup device is enabled for the associated pta pin. for port a pins that are con?ured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port a bit n. 1 internal pullup device enabled for port a bit n. 76543210 r 00 ptase5 1 1 ptase5 has no effect on the input-only pta5 pin. ptase4 ptase3 ptase2 ptase1 ptase0 w reset: 00111111 figure 6-5. slew rate enable for port a register (ptase) table 6-4. ptase register field descriptions field description 5:0 ptase[5:0] output slew rate enable for port a bits each of these control bits determines if the output slew rate control is enabled for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n. 4 datasheet u .com chapter 6 parallel input/output control MC9S08QD4 data sheet, rev. 1 72 freescale semiconductor 6.4.2.3 port a drive strength select (ptads) an output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (ptadsn). when high drive is selected a pin is capable of sourcing and sinking greater current. even though every i/o pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded. drive strength selection is intended to affect the dc behavior of i/o pins. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this the emc emissions may be affected by enabling pins as high drive. 6.4.2.4 port a drive strength select (ptads) 76543210 r 00 ptads5 1 1 ptads5 has no effect on the input-only pta5 pin. ptads4 ptads3 ptads2 ptads1 ptads0 w reset: 00000000 figure 6-6. drive strength selection for port a register (ptads) table 6-5. ptads register field descriptions field description 5:0 ptads[5:0] output drive strength selection for port a bits each of these control bits selects between low and high output drive for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port a bit n. 1 high output drive strength selected for port a bit n. 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 73 chapter 7 central processor unit (s08cpuv2) 7.1 introduction this section provides summary information about the registers, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code-compatible with the m68hc08 cpu. several instructions and enhanced addressing modes were added to improve c compiler ef?iency and to support a new background debug system which replaces the monitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: object code fully upward-compatible with m68hc05 and m68hc08 families all registers and memory are mapped to a single 64-kbyte address space 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) 16-bit index register (h:x) with powerful indexed addressing modes 8-bit accumulator (a) many instructions treat x as a second general-purpose 8-bit register seven addressing modes: inherent ?operands in internal registers relative ?8-bit signed offset to branch destination immediate ?operand in next object code byte(s) direct ?operand in memory at 0x0000?x00ff extended ?operand anywhere in 64-kbyte address space indexed relative to h:x ?five submodes including auto increment indexed relative to sp ?improves c ef?iency dramatically memory-to-memory data move instructions with four address mode combinations over?w, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ef?ient bit manipulation instructions fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions stop and wait instructions to invoke low-power operating modes 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 74 freescale semiconductor 7.2 programmer s model and cpu registers figure 7-1 shows the ve cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit register. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu results are often stored into the a accumulator after arithmetic and logical operations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of a can be stored to memory using various addressing modes to specify the address where data from a will be stored. reset has no effect on the contents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit registers (h and x), which often work together as a 16-bit address pointer where h holds the upper byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8-bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or transferred to a where arithmetic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is forced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 75 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available location on the automatic last-in-?st-out (lifo) stack. the stack may be located anywhere in the 64-kbyte address space that has ram and can be any size up to the amount of available ram. the stack is used to automatically save the return address for subroutine calls, the return address and cpu registers during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ram (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was included for compatibility with the m68hc05 family and is seldom used in new hcs08 programs because it only affects the low-order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. this is called a change-of-?w. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the ?st instruction that will be executed after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contains the interrupt mask (i) and ve ?gs that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code bits in general terms. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1. 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 76 freescale semiconductor figure 7-2. condition code register table 7-1. ccr register field descriptions field description 7 v two s complement over?w flag the cpu sets the over?w ?g when a two s complement over?w occurs. the signed branch instructions bgt, bge, ble, and blt use the over?w ?g. 0 no over?w 1 over?w 4 h half-carry flag the cpu sets the half-carry ?g when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry ?g is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ?when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the ?st instruction of the interrupt service routine is executed. interrupts are not recognized at the instruction boundary after any instruction that clears i (cli or tap). this ensures that the next instruction after a cli or tap will always be executed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ?the cpu sets the negative ?g when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most signi?ant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ?the cpu sets the zero ?g when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1 zero result 0 c carry/borrow flag the cpu sets the carry/borrow ?g when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow ?g. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow 70 ccr c v11hinz 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 77 7.3 addressing modes addressing modes de?e the way the cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/output (i/o) ports share a single 64-kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access variables in ram can also be used to access i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and dbnz use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. for brclr, brset, cbeq, and dbnz, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination location for branch instructions. a signed 8-bit offset value is located in the memory location immediately following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. in the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?x00ff). during execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory ef?ient than specifying a complete 16-bit address for the operand. 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 78 freescale semiconductor 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte ?st). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including ve that use the 16-bit h:x index register pair and two that use the stack pointer as the base reference. 7.3.6.1 indexed, no offset (ix) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 79 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special operations that are similar to instructions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop and wait directly affect other mcu circuitry. this section provides additional information about these operations. 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determines the source, refer to the resets, interrupts, and system con?uration chapter. the reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0xfffe and 0xffff and to ?l the instruction queue in preparation for execution of the ?st program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program information starting at the address indicated by the interrupt vector to ?l the instruction queue in preparation for execution of the ?st instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routine. although it is possible to clear the i bit with an instruction in the 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 80 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are dif?ult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the high-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt sequence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a hardware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumption while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event occurs, the cpu clocks will resume and the interrupt or reset event will be processed normally. if a serial background command is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. in such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be con?ured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodic signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial background command is issued to the mcu through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode depends on the particular hcs08 and whether the oscillator was stopped in stop mode. refer to the modes of operation chapter for more details. 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 81 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compared to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to stop processing user instructions and enter the active background mode. the only way to resume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program reaches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program. 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 82 freescale semiconductor 7.5 hcs08 instruction set summary instruction set summary nomenclature the nomenclature listed here is used in the instruction descriptions in table 7-2 . operators ( ) = contents of register or memory location shown inside parentheses = is loaded with (read: ?ets? &= boolean and |= boolean or = boolean exclusive-or = multiply = divide := concatenate += add ? negate (two s complement) cpu registers a= accumulator ccr = condition code register h= index register, higher order (most signi?ant) 8 bits x= index register, lower order (least signi?ant) 8 bits pc = program counter pch = program counter, higher order (most signi?ant) 8 bits pcl = program counter, lower order (least signi?ant) 8 bits sp = stack pointer memory and addressing m = a memory location or absolute data, depending on addressing mode m:m + 0x0001= a 16-bit value in two consecutive memory locations. the higher-order (most signi?ant) 8 bits are located at the address of m, and the lower-order (least signi?ant) 8 bits are located at the next higher sequential address. condition code register (ccr) bits v= two s complement over?w indicator, bit 7 h= half carry, bit 4 i= interrupt mask, bit 3 n= negative indicator, bit 2 z= zero indicator, bit 1 c= carry/borrow, bit 0 (carry out of bit 7) ccr activity notation ? bit not affected 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 83 0= bit forced to 0 1= bit forced to 1 = bit set or cleared according to results of operation u= unde?ed after the operation machine coding notation dd = low-order 8 bits of a direct address 0x0000?x00ff (high byte assumed to be 0x00) ee = upper 8 bits of 16-bit offset ff = lower 8 bits of 16-bit offset or 8-bit offset ii = one byte of immediate data jj = high-order byte of a 16-bit immediate data value kk = low-order byte of a 16-bit immediate data value hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr = relative offset source form everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the assembly source ?e exactly as shown. the initial 3- to 5-letter mnemonic is always a literal expression. all commas, pound signs (#), parentheses, and plus signs (+) are literal characters. n any label or expression that evaluates to a single integer in the range 0? opr8i any label or expression that evaluates to an 8-bit immediate value opr16i any label or expression that evaluates to a 16-bit immediate value opr8a any label or expression that evaluates to an 8-bit value. the instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64-kbyte address space (0x00xx). opr16a any label or expression that evaluates to a 16-bit value. the instruction treats this value as an address in the 64-kbyte address space. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 any label or expression that evaluates to a 16-bit value. because the hcs08 has a 16-bit address bus, this can be either a signed or an unsigned value. rel any label or expression that refers to an address that is within ?28 to +127 locations from the next address after the last byte of object code for the current instruction. the assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. address modes inh = inherent (no operands) imm = 8-bit or 16-bit immediate dir = 8-bit direct ext = 16-bit extended 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 84 freescale semiconductor ix = 16-bit indexed no offset ix+ = 16-bit indexed no offset, post increment (cbeq and mov only) ix1 = 16-bit indexed with 8-bit offset from h:x ix1+ = 16-bit indexed with 8-bit offset, post increment (cbeq only) ix2 = 16-bit indexed with 16-bit offset from h:x rel = 8-bit relative offset sp1 = stack pointer with 8-bit offset sp2 = stack pointer with 16-bit offset table 7-2. hcs08 instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc adc # opr8i adc opr8a adc opr16a adc oprx16 ,x adc oprx8 ,x adc ,x adc oprx16 ,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) ?? ??? imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9ed9 9ee9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 add # opr8i add opr8a add opr16a add oprx16 ,x add oprx8 ,x add ,x add oprx16 ,sp add oprx8 ,sp add without carry a (a) + (m) ?? ??? imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9edb 9eeb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ais # opr8i add immediate value (signed) to stack pointer sp (sp) + (m) m is sign extended to a 16-bit value imm a7 ii 2 aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) m is sign extended to a 16-bit value imm af ii 2 and # opr8i and opr8a and opr16a and oprx16 ,x and oprx8 ,x and ,x and oprx16 ,sp and oprx8 ,sp logical and a (a) & (m) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9ed4 9ee4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) ? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,sp arithmetic shift right ? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 5 1 1 5 4 6 bcc rel branch if carry bit clear branch if (c) = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 85 bclr n , opr8a clear bit n in memory mn 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) branch if (c) = 1 rel 25 rr 3 beq rel branch if equal branch if (z) = 1 rel 27 rr 3 bge rel branch if greater than or equal to (signed operands) branch if (n v ) = 0 rel 90 rr 3 bgnd enter active background if enbdm = 1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ bgt rel branch if greater than (signed operands) branch if (z) | (n v ) = 0 rel 92 rr 3 bhcc rel branch if half carry bit clear branch if (h) = 0 rel 28 rr 3 bhcs rel branch if half carry bit set branch if (h) = 1 rel 29 rr 3 bhi rel branch if higher branch if (c) | (z) = 0 rel 22 rr 3 bhs rel branch if higher or same (same as bcc) branch if (c) = 0 rel 24 rr 3 bih rel branch if irq pin high branch if irq pin = 1 rel 2f rr 3 bil rel branch if irq pin low branch if irq pin = 0 rel 2e rr 3 bit # opr8i bit opr8a bit opr16a bit oprx16 ,x bit oprx8 ,x bit ,x bit oprx16 ,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9ed5 9ee5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ble rel branch if less than or equal to (signed operands) branch if (z) | (n v ) = 1 rel 93 rr 3 blo rel branch if lower (same as bcs) branch if (c) = 1 rel 25 rr 3 bls rel branch if lower or same branch if (c) | (z) = 1 rel 23 rr 3 blt rel branch if less than (signed operands) branch if (n v ) = 1 rel 91 rr 3 bmc rel branch if interrupt mask clear branch if (i) = 0 rel 2c rr 3 bmi rel branch if minus branch if (n) = 1 rel 2b rr 3 bms rel branch if interrupt mask set branch if (i) = 1 rel 2d rr 3 bne rel branch if not equal branch if (z) = 0 rel 26 rr 3 bpl rel branch if plus branch if (n) = 0 rel 2a rr 3 bra rel branch always no test rel 20 rr 3 table 7-2. hcs08 instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 86 freescale semiconductor brclr n , opr8a , rel branch if bit n in memory clear branch if (mn) = 0 ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never uses 3 bus cycles rel 21 rr 3 brset n , opr8a , rel branch if bit n in memory set branch if (mn) = 1 ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr8a set bit n in memory mn 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 0x0002 push (pcl); sp (sp) ?0x0001 push (pch); sp (sp) ?0x0001 pc (pc) + rel rel ad rr 5 cbeq opr8a , rel cbeqa # opr8i , rel cbeqx # opr8i , rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and branch if equal branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 clc clear carry bit c 0 ? inh 98 1 cli clear interrupt mask bit i 0 0 inh 9a 1 clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m 0x00 a 0x00 x 0x00 h 0x00 m 0x00 m 0x00 m 0x00 001 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 5 1 1 1 5 4 6 cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory (a) ?(m) (ccr updated but operands not changed) ? ??? imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9ed1 9ee1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement (one? complement) m ( m)= 0xff ?(m) a ( a) = 0xff ?(a) x ( x) = 0xff ?(x) m ( m) = 0xff ?(m) m ( m) = 0xff ?(m) m ( m) = 0xff ?(m) 0 ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 5 1 1 5 4 6 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ?(m:m + 0x0001) (ccr updated but operands not changed) ? ??? ext imm dir sp1 3e 65 75 9ef3 hh ll jj kk dd ff 6 3 5 6 table 7-2. hcs08 instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 87 cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory (x) ?(m) (ccr updated but operands not changed) ? ??? imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9ed3 9ee3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 daa decimal adjust accumulator after add or adc of bcd values (a) 10 u ??? inh 72 1 dbnz opr8a , rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement and branch if not zero decrement a, x, or m branch if (result) 0 dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ?0x01 a (a) ?0x01 x (x) ?0x01 m (m) ?0x01 m (m) ?0x01 m (m) ?0x01 ? ?? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 5 1 1 5 4 6 div divide a (h:a) (x) h remainder ?? inh 52 6 eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9ed8 9ee8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + 0x01 a (a) + 0x01 x (x) + 0x01 m (m) + 0x01 m (m) + 0x01 m (m) + 0x01 ? ?? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 5 1 1 5 4 6 jmp opr8a jmp opr16a jmp oprx16 ,x jmp oprx8 ,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ?0x0001 push (pch); sp (sp) ?0x0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 lda # opr8i lda opr8a lda opr16a lda oprx16 ,x lda oprx8 ,x lda ,x lda oprx16 ,sp lda oprx8 ,sp load accumulator from memory a (m) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9ed6 9ee6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16 ,x ldhx oprx8 ,x ldhx oprx8 ,sp load index register (h:x) from memory h:x ( m:m + 0x0001 ) 0 ?? imm dir ext ix ix2 ix1 sp1 45 55 32 9eae 9ebe 9ece 9efe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 table 7-2. hcs08 instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 88 freescale semiconductor ldx # opr8i ldx opr8a ldx opr16a ldx oprx16 ,x ldx oprx8 ,x ldx ,x ldx oprx16 ,sp ldx oprx8 ,sp load x (index register low) from memory x (m) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9ede 9eee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 lsl opr8a lsla lslx lsl oprx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) ? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right ? 0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 5 1 1 5 4 6 mov opr8a , opr8a mov opr8a ,x+ mov # opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source h:x (h:x) + 0x0001 in ix+/dir and dir/ix+ modes 0 ?? dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 mul unsigned multiply x:a (x) (a) ?? inh 42 5 neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate (two? complement) m ?(m) = 0x00 ?(m) a ?(a) = 0x00 ?(a) x ?(x) = 0x00 ?(x) m ?(m) = 0x00 ?(m) m ?(m) = 0x00 ?(m) m ?(m) = 0x00 ?(m) ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 5 1 1 5 4 6 nop no operation uses 1 bus cycle inh 9d 1 nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) 0 ?? imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9eda 9eea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 psha push accumulator onto stack push (a); sp (sp ) 0x0001 inh 87 2 pshh push h (index register high) onto stack push (h) ; sp (sp ) 0x0001 inh 8b 2 pshx push x (index register low) onto stack push (x) ; sp (sp ) 0x0001 inh 89 2 pula pull accumulator from stack sp (sp + 0x0001); pull ( a ) inh 86 3 pulh pull h (index register high) from stack sp (sp + 0x0001); pull ( h ) inh 8a 3 pulx pull x (index register low) from stack sp (sp + 0x0001); pull ( x ) inh 88 3 rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry ? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 5 1 1 5 4 6 table 7-2. hcs08 instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc c b0 b7 0 b0 b7 c 0 c b0 b7 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 89 ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry ? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 5 1 1 5 4 6 rsp reset stack pointer sp 0xff (high byte not affected) inh 9c 1 rti return from interrupt sp (sp) + 0x0001; pull (ccr) sp (sp) + 0x0001; pull (a) sp (sp) + 0x0001; pull (x) sp (sp) + 0x0001; pull (pch) sp (sp) + 0x0001; pull (pcl) ?????? inh 80 9 rts return from subroutine sp sp + 0x0001 ; pull ( pch) sp sp + 0x0001; pull (pcl) inh 81 6 sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ?(m) ?(c) ? ??? imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9ed2 9ee2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 sec set carry bit c 1 ? inh 99 1 sei set interrupt mask bit i 1 1 inh 9b 1 sta opr8a sta opr16a sta oprx16 ,x sta oprx8 ,x sta ,x sta oprx16 ,sp sta oprx8 ,sp store accumulator in memory m (a) 0 ?? dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9ed7 9ee7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + 0x0001) (h:x) 0 ?? dir ext sp1 35 96 9eff dd hh ll ff 4 5 5 stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing 0 inh 8e 2+ stx opr8a stx opr16a stx oprx16 ,x stx oprx8 ,x stx ,x stx oprx16 ,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) 0 ?? dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9edf 9eef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) (m) ? ??? imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9ed0 9ee0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 swi software interrupt pc (pc) + 0x0001 push (pcl); sp (sp) ?0x0001 push (pch); sp (sp) ?0x0001 push (x); sp (sp) ?0x0001 push (a); sp (sp) ?0x0001 push (ccr); sp (sp) ?0x0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte 1 inh 83 11 table 7-2. hcs08 instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc b0 b7 c 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 90 freescale semiconductor tap transfer accumulator to ccr ccr (a) ?????? inh 84 1 tax transfer accumulator to x (index register low) x (a) inh 97 1 tpa transfer ccr to accumulator a (ccr) inh 85 1 tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ?0x00 (a) ?0x00 (x) ?0x00 (m) ?0x00 (m) ?0x00 (m) ?0x00 0 ?? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 4 1 1 4 3 5 tsx transfer sp to index reg. h:x (sp) + 0x0001 inh 95 2 txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 txs transfer index reg. to sp sp (h:x) ?0x0001 inh 94 2 wait enable interrupts; wait for interrupt i bit 0; halt cpu 0 inh 8f 2+ 1 bus clock frequency is one-half of the cpu clock frequency. table 7-2. hcs08 instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand bus cycles 1 vh i nzc 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 91 table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modify-write control register/memory 00 5 brset0 3 dir 10 5 bset0 2 dir 20 3 bra 2 rel 30 5 neg 2 dir 40 1 nega 1 inh 50 1 negx 1 inh 60 5 neg 2 ix1 70 4 neg 1ix 80 9 rti 1 inh 90 3 bge 2 rel a0 2 sub 2 imm b0 3 sub 2 dir c0 4 sub 3 ext d0 4 sub 3 ix2 e0 3 sub 2 ix1 f0 3 sub 1ix 01 5 brclr0 3 dir 11 5 bclr0 2 dir 21 3 brn 2 rel 31 5 cbeq 3 dir 41 4 cbeqa 3 imm 51 4 cbeqx 3 imm 61 5 cbeq 3 ix1+ 71 5 cbeq 2 ix+ 81 6 rts 1 inh 91 3 blt 2 rel a1 2 cmp 2 imm b1 3 cmp 2 dir c1 4 cmp 3 ext d1 4 cmp 3 ix2 e1 3 cmp 2 ix1 f1 3 cmp 1ix 02 5 brset1 3 dir 12 5 bset1 2 dir 22 3 bhi 2 rel 32 5 ldhx 3 ext 42 5 mul 1 inh 52 6 div 1 inh 62 1 nsa 1 inh 72 1 daa 1 inh 82 5+ bgnd 1 inh 92 3 bgt 2 rel a2 2 sbc 2 imm b2 3 sbc 2 dir c2 4 sbc 3 ext d2 4 sbc 3 ix2 e2 3 sbc 2 ix1 f2 3 sbc 1ix 03 5 brclr1 3 dir 13 5 bclr1 2 dir 23 3 bls 2 rel 33 5 com 2 dir 43 1 coma 1 inh 53 1 comx 1 inh 63 5 com 2 ix1 73 4 com 1ix 83 11 swi 1 inh 93 3 ble 2 rel a3 2 cpx 2 imm b3 3 cpx 2 dir c3 4 cpx 3 ext d3 4 cpx 3 ix2 e3 3 cpx 2 ix1 f3 3 cpx 1ix 04 5 brset2 3 dir 14 5 bset2 2 dir 24 3 bcc 2 rel 34 5 lsr 2 dir 44 1 lsra 1 inh 54 1 lsrx 1 inh 64 5 lsr 2 ix1 74 4 lsr 1ix 84 1 ta p 1 inh 94 2 txs 1 inh a4 2 and 2 imm b4 3 and 2 dir c4 4 and 3 ext d4 4 and 3 ix2 e4 3 and 2 ix1 f4 3 and 1ix 05 5 brclr2 3 dir 15 5 bclr2 2 dir 25 3 bcs 2 rel 35 4 sthx 2 dir 45 3 ldhx 3 imm 55 4 ldhx 2 dir 65 3 cphx 3 imm 75 5 cphx 2 dir 85 1 tpa 1 inh 95 2 tsx 1 inh a5 2 bit 2 imm b5 3 bit 2 dir c5 4 bit 3 ext d5 4 bit 3 ix2 e5 3 bit 2 ix1 f5 3 bit 1ix 06 5 brset3 3 dir 16 5 bset3 2 dir 26 3 bne 2 rel 36 5 ror 2 dir 46 1 rora 1 inh 56 1 rorx 1 inh 66 5 ror 2 ix1 76 4 ror 1ix 86 3 pula 1 inh 96 5 sthx 3 ext a6 2 lda 2 imm b6 3 lda 2 dir c6 4 lda 3 ext d6 4 lda 3 ix2 e6 3 lda 2 ix1 f6 3 lda 1ix 07 5 brclr3 3 dir 17 5 bclr3 2 dir 27 3 beq 2 rel 37 5 asr 2 dir 47 1 asra 1 inh 57 1 asrx 1 inh 67 5 asr 2 ix1 77 4 asr 1ix 87 2 psha 1 inh 97 1 ta x 1 inh a7 2 ais 2 imm b7 3 sta 2 dir c7 4 sta 3 ext d7 4 sta 3 ix2 e7 3 sta 2 ix1 f7 2 sta 1ix 08 5 brset4 3 dir 18 5 bset4 2 dir 28 3 bhcc 2 rel 38 5 lsl 2 dir 48 1 lsla 1 inh 58 1 lslx 1 inh 68 5 lsl 2 ix1 78 4 lsl 1ix 88 3 pulx 1 inh 98 1 clc 1 inh a8 2 eor 2 imm b8 3 eor 2 dir c8 4 eor 3 ext d8 4 eor 3 ix2 e8 3 eor 2 ix1 f8 3 eor 1ix 09 5 brclr4 3 dir 19 5 bclr4 2 dir 29 3 bhcs 2 rel 39 5 rol 2 dir 49 1 rola 1 inh 59 1 rolx 1 inh 69 5 rol 2 ix1 79 4 rol 1ix 89 2 pshx 1 inh 99 1 sec 1 inh a9 2 adc 2 imm b9 3 adc 2 dir c9 4 adc 3 ext d9 4 adc 3 ix2 e9 3 adc 2 ix1 f9 3 adc 1ix 0a 5 brset5 3 dir 1a 5 bset5 2 dir 2a 3 bpl 2 rel 3a 5 dec 2 dir 4a 1 deca 1 inh 5a 1 decx 1 inh 6a 5 dec 2 ix1 7a 4 dec 1ix 8a 3 pulh 1 inh 9a 1 cli 1 inh aa 2 ora 2 imm ba 3 ora 2 dir ca 4 ora 3 ext da 4 ora 3 ix2 ea 3 ora 2 ix1 fa 3 ora 1ix 0b 5 brclr5 3 dir 1b 5 bclr5 2 dir 2b 3 bmi 2 rel 3b 7 dbnz 3 dir 4b 4 dbnza 2 inh 5b 4 dbnzx 2 inh 6b 7 dbnz 3 ix1 7b 6 dbnz 2ix 8b 2 pshh 1 inh 9b 1 sei 1 inh ab 2 add 2 imm bb 3 add 2 dir cb 4 add 3 ext db 4 add 3 ix2 eb 3 add 2 ix1 fb 3 add 1ix 0c 5 brset6 3 dir 1c 5 bset6 2 dir 2c 3 bmc 2 rel 3c 5 inc 2 dir 4c 1 inca 1 inh 5c 1 incx 1 inh 6c 5 inc 2 ix1 7c 4 inc 1ix 8c 1 clrh 1 inh 9c 1 rsp 1 inh bc 3 jmp 2 dir cc 4 jmp 3 ext dc 4 jmp 3 ix2 ec 3 jmp 2 ix1 fc 3 jmp 1ix 0d 5 brclr6 3 dir 1d 5 bclr6 2 dir 2d 3 bms 2 rel 3d 4 tst 2 dir 4d 1 tsta 1 inh 5d 1 tstx 1 inh 6d 4 tst 2 ix1 7d 3 tst 1ix 9d 1 nop 1 inh ad 5 bsr 2 rel bd 5 jsr 2 dir cd 6 jsr 3 ext dd 6 jsr 3 ix2 ed 5 jsr 2 ix1 fd 5 jsr 1ix 0e 5 brset7 3 dir 1e 5 bset7 2 dir 2e 3 bil 2 rel 3e 6 cphx 3 ext 4e 5 mov 3dd 5e 5 mov 2 dix+ 6e 4 mov 3 imd 7e 5 mov 2 ix+d 8e 2+ stop 1 inh 9e page 2 ae 2 ldx 2 imm be 3 ldx 2 dir ce 4 ldx 3 ext de 4 ldx 3 ix2 ee 3 ldx 2 ix1 fe 3 ldx 1ix 0f 5 brclr7 3 dir 1f 5 bclr7 2 dir 2f 3 bih 2 rel 3f 5 clr 2 dir 4f 1 clra 1 inh 5f 1 clrx 1 inh 6f 5 clr 2 ix1 7f 4 clr 1ix 8f 2+ wait 1 inh 9f 1 txa 1 inh af 2 aix 2 imm bf 3 stx 2 dir cf 4 stx 3 ext df 4 stx 3 ix2 ef 3 stx 2 ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode 4 datasheet u .com chapter 7 central processor unit (s08cpuv2) MC9S08QD4 data sheet, rev. 1 92 freescale semiconductor bit-manipulation branch read-modify-write control register/memory 9e60 6 neg 3 sp1 9ed0 5 sub 4 sp2 9ee0 4 sub 3 sp1 9e61 6 cbeq 4 sp1 9ed1 5 cmp 4 sp2 9ee1 4 cmp 3 sp1 9ed2 5 sbc 4 sp2 9ee2 4 sbc 3 sp1 9e63 6 com 3 sp1 9ed3 5 cpx 4 sp2 9ee3 4 cpx 3 sp1 9ef3 6 cphx 3 sp1 9e64 6 lsr 3 sp1 9ed4 5 and 4 sp2 9ee4 4 and 3 sp1 9ed5 5 bit 4 sp2 9ee5 4 bit 3 sp1 9e66 6 ror 3 sp1 9ed6 5 lda 4 sp2 9ee6 4 lda 3 sp1 9e67 6 asr 3 sp1 9ed7 5 sta 4 sp2 9ee7 4 sta 3 sp1 9e68 6 lsl 3 sp1 9ed8 5 eor 4 sp2 9ee8 4 eor 3 sp1 9e69 6 rol 3 sp1 9ed9 5 adc 4 sp2 9ee9 4 adc 3 sp1 9e6a 6 dec 3 sp1 9eda 5 ora 4 sp2 9eea 4 ora 3 sp1 9e6b 8 dbnz 4 sp1 9edb 5 add 4 sp2 9eeb 4 add 3 sp1 9e6c 6 inc 3 sp1 9e6d 5 tst 3 sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4 ix2 9ece 5 ldhx 3 ix1 9ede 5 ldx 4 sp2 9eee 4 ldx 3 sp1 9efe 5 ldhx 3 sp1 9e6f 6 clr 3 sp1 9edf 5 stx 4 sp2 9eef 4 stx 3 sp1 9eff 5 sthx 3 sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3 sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2) 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 93 chapter 8 analog-to-digital converter (adc10v1) 8.1 introduction the 10-bit analog-to-digital converter (adc) is a successive approximation adc designed for operation within an integrated microcontroller system-on-chip. the adc module design supports up to 28 separate analog inputs (ad0-ad27). only four (adc1p0?dc1p3) of the possible inputs are implemented on the MC9S08QD4 mcu. these inputs are selected by the adch bits. 4 datasheet u .com chapter 8 analog-to-digital converter (adc10v1) MC9S08QD4 data sheet, rev. 1 94 freescale semiconductor figure 8-1. MC9S08QD4 block diagram highlighting adc block and pins notes: 1 port pins are software con?urable with pullup device if input port. 2 port pins are software con?urable for output drive strength. 3 port pins are software con?urable for output slew rate control. 4 irq contains a software con?urable (irqpdd) pullup/pulldown device if pta5 enabled as irq pin function (irqpe = 1). 5 reset contains integrated pullup device if pta5 enabled as reset pin function (rstpe = 1). 6 pta5 does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 7 pta4 contains integrated pullup device if bkgd enabled (bkgdpe = 1). 8 when pin functions as kbi (kbipen = 1) and associated pin is con?ured to enable the pullup device, kbedgn can be used to recon?ure the pullup as a pulldown device. user ram hcs08 core cpu bdc 2-ch 16-bit timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management rti cop irq lvd voltage regulator port a pta5/tpm2ch0i/irq/ reset pta4/tpm2ch0o/bkgd/ms pta3/kbi1p3/tclk2/adc1p3 pta2/kbi1p2/tclk1/adc1p2 pta1/kbi1p1/tpm1ch1/adc1p1 pta0/kbi1p0/tpm1ch0/adc1p0 4-bit keyboard interrupt module (kbi) 256 bytes 16-mhz internal clock source (ics) v ss v dd v ssa v dda v refl v refh 4 analog-to-digital converter (adc) 10-bit tpm1ch0 tpm1ch1 bkgd/ms irq 4 1-ch 16-bit timer/pwm module (tpm2) tpm2ch0 user flash 4096 bytes tclk2 tclk1 4 datasheet u .com chapter 8 analog-to-digital converter (adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 95 8.1.1 module con?urations this section provides device-speci? information for con?uring the adc on MC9S08QD4. 8.1.1.1 channel assignments the adc channel assignments for the MC9S08QD4 devices are shown in table 8-1 . reserved channels convert to an unknown value. 8.1.1.2 alternate clock the adc is capable of performing conversions using the mcu bus clock, the bus clock divided by two, or the local asynchronous clock (adack) within the module. the alternate clock, altclk, input for the MC9S08QD4 mcu devices is not implemented. 8.1.1.3 hardware trigger the adc hardware trigger, adhwt, is output from the real-time interrupt (rti) counter. the rti counter can be clocked by either icserclk or a nominal 32-khz clock source within the rti block. table 8-1. adc channel assignment adch channel input pin control adch channel input pin control 00000 ad0 pta0/adc1p0 adpc0 10000 ad16 v ss n/a 00001 ad1 pta1/adc1p1 adpc1 10001 ad17 v ss n/a 00010 ad2 pta2/adc1p2 adpc2 10010 ad18 v ss n/a 00011 ad3 pta3/adc1p3 adpc3 10011 ad19 v ss n/a 00100 ad4 vss n/a 10100 ad20 v ss n/a 00101 ad5 vss n/a 10101 ad21 v ss n/a 00110 ad6 vss n/a 10110 ad22 reserved n/a 00111 ad7 vss n/a 10111 ad23 reserved n/a 01000 ad8 v ss n/a 11000 ad24 reserved n/a 01001 ad9 v ss n/a 11001 ad25 reserved n/a 01010 ad10 v ss n/a 11010 ad26 temperature sensor 1 1 for information, see section 8.1.1.5, ?emperature sensor ? n/a 01011 ad11 v ss n/a 11011 ad27 internal bandgap 2 2 requires bgbe =1 in spmsc1 see section 5.8.8, ?ystem power management status and control 1 register (spmsc1) ? for value of bandgap voltage reference see section a.5, ?c characteristics ? n/a 01100 ad12 v ss n/a 11100 v refh v dd n/a 01101 ad13 v ss n/a 11101 v refh v dd n/a 01110 ad14 v ss n/a 11110 v refl v ss n/a 01111 ad15 v ss n/a 11111 module disabled none n/a 4 datasheet u .com chapter 8 analog-to-digital converter (adc10v1) MC9S08QD4 data sheet, rev. 1 96 freescale semiconductor the period of the rti is determined by the input clock frequency and the rtis bits. the rti counter is a free running counter that generates an over?w at the rti rate determined by the rtis bits. when the adc hardware trigger is enabled, a conversion is initiated upon a rti counter over?w. the rti can be con?ured to cause a hardware trigger in mcu run, wait, and stop3. 8.1.1.4 analog pin enables the adc on MC9S08QD4 contains only one analog pin enable register, apctl1. 8.1.1.5 temperature sensor to use the on-chip temperature sensor, the user must perform the following: con?ure adc for long sample with a maximum of 1-mhz clock convert the bandgap voltage reference channel (ad27) by converting the digital value of the bandgap voltage reference channel using the value of v bg the user can determine v dd . for value of bandgap voltage, see section a.5, ?c characteristics ? convert the temperature sensor channel (ad26) by using the calculated value of v dd , convert the digital value of ad26 into a voltage, v temp equation 8-1 provides an approximate transfer function of the on-chip temperature sensor for v dd = 3.0v, temp = 25 c, using the adc at f adck = 1.0mhz and con?ured for long sample. temp c = 25 ((v temp ?0.7013) / ( 0.0017)) eqn. 8-1 0.0017 is the uncalibrated voltage versus temperature slope in v/ c. uncalibrated accuracy of the temperature sensor is approximately 12 c, using equation 8-1 . to improve accuracy the user should calibrate the bandgap voltage reference and temperature sensor. calibrating at 25 c will improve accuracy to 4.5 c. calibration at 3 points, -40 c, 25 c and 105 c will improve accuracy to 2.5 c. once calibration has been completed, the user will need to calculate the slope for both hot and cold. in application code, the user would then calculate the temperature using equation 8-1 as detailed above and then determine if the temperature is above or below 25 c. once determined if the temperature is above or below 25 c, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. 8.1.1.6 low-power mode operation the adc is capable of running in stop3 mode but requires lvdse in spmsc1 to be set. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 97 8.1.2 features features of the adc module include: linear successive approximation algorithm with 10 bits resolution. up to 28 analog inputs. output formatted in 10- or 8-bit right-justi?d format. single or continuous conversion (automatic return to idle after single conversion). con?urable sample time and conversion speed/power. conversion complete ?g and interrupt. input clock selectable from up to four sources. operation in wait or stop3 modes for lower noise operation. asynchronous clock source for lower noise operation. selectable asynchronous hardware conversion trigger. automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 8.1.3 block diagram figure 8-2 provides a block diagram of the adc module 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 98 freescale semiconductor figure 8-2. adc block diagram 8.2 external signal description the adc module supports up to 28 separate analog inputs. it also requires four supply/reference/ground connections. table 8-2. signal properties name function ad27?d0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ?? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adccfg adcsc1 adcsc2 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 99 8.2.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external ?tering may be necessary to ensure clean v ddad for good results. 8.2.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 8.2.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter. in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad , or may be driven by an external source that is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 8.2.4 voltage reference low (v refl ) v refl is the low reference voltage for the converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 8.2.5 analog channel inputs (adx) the adc module supports up to 28 separate analog inputs. an input is selected for conversion through the adch channel select bits. 8.3 register de?ition these memory mapped registers control and monitor operation of the adc: status and control register, adcsc1 status and control register, adcsc2 data result registers, adcrh and adcrl compare value registers, adccvh and adccvl con?uration register, adccfg pin enable registers, apctl1, apctl2, apctl3 8.3.1 status and control register 1 (adcsc1) this section describes the function of the adc status and control register (adcsc1). writing adcsc1 aborts the current conversion and initiates a new conversion (if the adch bits are equal to a value other than all 1s). 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 100 freescale semiconductor 7654 3 210 r coco aien adco adch w reset: 0 0 0 1 1 1 1 1 = unimplemented or reserved figure 8-3. status and control register (adcsc1) table 8-3. adcsc1 register field descriptions field description 7 coco conversion complete flag ?the coco ?g is a read-only bit which is set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compare function is enabled (acfe = 1) the coco ?g is set upon completion of a conversion only if the compare result is true. this bit is cleared whenever adcsc1 is written or whenever adcrl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable ?aien is used to enable conversion complete interrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable ?adco is used to enable continuous conversions. 0 one conversion following a write to the adcsc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adcsc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select the adch bits form a 5-bit ?ld which is used to select one of the input channels. the input channels are detailed in figure 8-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set to 1. this feature allows for explicit disabling of the adc and isolation of the input channel from all sources. terminating continuous conversions this way will prevent an additional, single conversion from being performed. it is not necessary to set the channel select bits to all 1s to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. figure 8-4. input channel select adch input select adch input select 00000 ad0 10000 ad16 00001 ad1 10001 ad17 00010 ad2 10010 ad18 00011 ad3 10011 ad19 00100 ad4 10100 ad20 00101 ad5 10101 ad21 00110 ad6 10110 ad22 00111 ad7 10111 ad23 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 101 8.3.2 status and control register 2 (adcsc2) the adcsc2 register is used to control the compare function, conversion trigger and conversion active of the adc module. figure 8-5. status and control register 2 (adcsc2) 01000 ad8 11000 ad24 01001 ad9 11001 ad25 01010 ad10 11010 ad26 01011 ad11 11011 ad27 01100 ad12 11100 reserved 01101 ad13 11101 v refh 01110 ad14 11110 v refl 01111 ad15 11111 module disabled 7654 3 210 radact adtrg acfe acfgt 00 r 1 1 bits 1 and 0 are reserved bits that must always be written to 0. r 1 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved table 8-4. adcsc2 register field descriptions field description 7 adact conversion active ?adact indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select adtrg is used to select the type of trigger to be used for initiating a conversion. two types of trigger are selectable: software trigger and hardware trigger. when software trigger is selected, a conversion is initiated following a write to adcsc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected figure 8-4. input channel select (continued) adch input select adch input select 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 102 freescale semiconductor 8.3.3 data result high register (adcrh) adcrh contains the upper two bits of the result of a 10-bit conversion. when con?ured for 8-bit conversions both adr8 and adr9 are equal to zero. adcrh is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until after the next conversion is completed, then the intermediate conversion result will be lost. in 8-bit mode there is no interlocking with adcrl. in the case that the mode bits are changed, any data in adcrh becomes invalid. 8.3.4 data result low register (adcrl) adcrl contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until the after next conversion is completed, then the intermediate conversion results will be lost. in 8-bit mode, there is no interlocking with adcrh. in the case that the mode bits are changed, any data in adcrl becomes invalid. 5 acfe compare function enable ?acfe is used to enable the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable acfgt is used to con?ure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare level 1 compare triggers when input is greater than or equal to compare level 7 654 3 210 r 0 0 0 0 0 0 adr9 adr8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 8-6. data result high register (adcrh) table 8-4. adcsc2 register field descriptions (continued) field description 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 103 8.3.5 compare value high register (adccvh) this register holds the upper two bits of the 10-bit compare value. these bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.in 8-bit operation, adccvh is not used during compare. 8.3.6 compare value low register (adccvl) this register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value. bits adcv7:adcv0 are compared to the lower 8 bits of the result following a conversion in either 10-bit or 8-bit mode. 8.3.7 con?uration register (adccfg) adccfg is used to select the mode of operation, clock source, clock divide, and con?ure for low power or long sample time. 7 654 3 210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 8-7. data result low register (adcrl) 7654 3 210 r0000 adcv9 adcv8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 8-8. compare value high register (adccvh) 7 654 3 210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset: 0 0 0 0 0 0 0 0 figure 8-9. compare value low register(adccvl) 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 104 freescale semiconductor 7654 3 210 r adlpc adiv adlsmp mode adiclk w reset: 0 0 0 0 0 0 0 0 figure 8-10. con?uration register (adccfg) table 8-5. adccfg register field descriptions field description 7 adlpc low power con?uration ?adlpc controls the speed and power con?uration of the successive approximation converter. this is used to optimize power consumption when higher sample rates are not required. 0 high speed con?uration 1 low power con?uration: {fc31}the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select ?adiv select the divide ratio used by the adc to generate the internal clock adck. table 8-6 shows the available clock con?urations. 4 adlsmp long sample time con?uration adlsmp selects between long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 short sample time 1 long sample time 3:2 mode conversion mode selection ?mode bits are used to select between 10- or 8-bit operation. see table 8-7 . 1:0 adiclk input clock select ?adiclk bits select the input clock source to generate the internal clock adck. see table 8-8 . table 8-6. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 8-7. conversion modes mode mode description 00 8-bit conversion (n=8) 01 reserved 10 10-bit conversion (n=10) 11 reserved 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 105 8.3.8 pin control 1 register (apctl1) the pin control registers are used to disable the i/o port control of mcu pins used as analog inputs. apctl1 is used to control the pins associated with channels 0? of the adc module. table 8-8. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w reset: 0 0 0 0 0 0 0 0 figure 8-11. pin control 1 register (apctl1) table 8-9. apctl1 register field descriptions field description 7 adpc7 adc pin control 7 ?adpc7 is used to control the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6 ?adpc6 is used to control the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled 5 adpc5 adc pin control 5 ?adpc5 is used to control the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4 ?adpc4 is used to control the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3 ?adpc3 is used to control the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2 ?adpc2 is used to control the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 106 freescale semiconductor 8.3.9 pin control 2 register (apctl2) apctl2 is used to control channels 8?5 of the adc module. 1 adpc1 adc pin control 1 ?adpc1 is used to control the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0 ?adpc0 is used to control the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset: 0 0 0 0 0 0 0 0 figure 8-12. pin control 2 register (apctl2) table 8-10. apctl2 register field descriptions field description 7 adpc15 adc pin control 15 ?adpc15 is used to control the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14 ?adpc14 is used to control the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13 ?adpc13 is used to control the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled 4 adpc12 adc pin control 12 ?adpc12 is used to control the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11 ?adpc11 is used to control the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10 ?adpc10 is used to control the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled table 8-9. apctl1 register field descriptions (continued) field description 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 107 8.3.10 pin control 3 register (apctl3) apctl3 is used to control channels 16?3 of the adc module. 1 adpc9 adc pin control 9 ?adpc9 is used to control the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8 ?adpc8 is used to control the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset: 0 0 0 0 0 0 0 0 figure 8-13. pin control 3 register (apctl3) table 8-11. apctl3 register field descriptions field description 7 adpc23 adc pin control 23 ?adpc23 is used to control the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22 ?adpc22 is used to control the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21 ?adpc21 is used to control the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20 ?adpc20 is used to control the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled 3 adpc19 adc pin control 19 ?adpc19 is used to control the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18 ?adpc18 is used to control the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled table 8-10. apctl2 register field descriptions (continued) field description 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 108 freescale semiconductor 8.4 functional description the adc module is disabled during reset or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to-digital conversion on any of the software selectable channels. the selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result. in 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is placed in the data registers (adcrh and adcrl).in 10-bit mode, the result is rounded to 10 bits and placed in adcrh and adcrl. in 8-bit mode, the result is rounded to 8 bits and placed in adcrl. the conversion complete ?g (coco) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare function is enabled by setting the acfe bit and operates in conjunction with any of the conversion modes and con?urations. 8.4.1 clock select and divide control one of four clock sources can be selected as the clock source for the adc module. this clock source is then divided by a con?urable value to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. the bus clock, which is equal to the frequency at which software is executed. this is the default selection following reset. the bus clock divided by 2. for higher bus clock rates, this allows a maximum divide by 16 of the bus clock. altclk, as de?ed for this mcu (see module section introduction). the asynchronous clock (adack) this clock is generated from a clock source within the adc module. when selected as the clock source this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selected, its frequency must fall within the speci?d frequency range for adck. if the available clocks are too slow, the adc will not perform according to speci?ations. if the available clocks 1 adpc17 adc pin control 17 ?adpc17 is used to control the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16 ?adpc16 is used to control the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled table 8-11. apctl3 register field descriptions (continued) field description 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 109 are too fast, then the clock must be divided to the appropriate frequency. this divider is speci?d by the adiv bits and can be divide-by 1, 2, 4, or 8. 8.4.2 input select and pin control the pin control registers (apctl3, apctl2, and apctl1) are used to disable the i/o port control of the pins used as analog inputs.when a pin control register bit is set, the following conditions are forced for the associated mcu pin: the output buffer is forced to its high impedance state. the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. the pullup is disabled. 8.4.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus. consult the module introduction for information on the adhwt source speci? to this mcu. when adhwt source is available and hardware trigger is enabled (adtrg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progress when a rising edge occurs, the rising edge is ignored. in continuous convert con?uration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and con?urations. 8.4.4 conversion control conversions can be performed in either 10-bit mode or 8-bit mode as determined by the mode bits. conversions can be initiated by either a software or hardware trigger. in addition, the adc module can be con?ured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value. 8.4.4.1 initiating conversions a conversion is initiated: following a write to adcsc1 (with adch bits not all 1s) if software triggered operation is selected. following a hardware trigger (adhwt) event if hardware triggered operation is selected. following the transfer of the result to the data registers when continuous conversion is enabled. if continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation, continuous conversions begin after adcsc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 110 freescale semiconductor 8.4.4.2 completing conversions a conversion is completed when the result of the conversion is transferred into the data result registers, adcrh and adcrl. this is indicated by the setting of coco. an interrupt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from overwriting previous data in adcrh and adcrl if the previous data is in the process of being read while in 12-bit or 10-bit mode (the adcrh register has been read but the adcrl register has not). when blocking is active, the data transfer is blocked, coco is not set, and the new result is lost. in the case of single conversions with the compare function enabled and the compare condition false, blocking has no effect and adc operation is terminated. in all other cases of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 8.4.4.3 aborting conversions any conversion in progress will be aborted when: a write to adcsc1 occurs (the current conversion will be aborted and a new conversion will be initiated, if adch are not all 1s). a write to adcsc2, adccfg, adccvh, or adccvl occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. the mcu is reset. the mcu enters stop mode with adack not enabled. when a conversion is aborted, the contents of the data registers, adcrh and adcrl, are not altered but continue to be the values transferred after the completion of the last successful conversion. in the case that the conversion was aborted by a reset, adcrh and adcrl return to their reset states. 8.4.4.4 power control the adc module remains in its idle state until a conversion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by setting adlpc. this results in a lower maximum value for f adck (see the electrical speci?ations). 8.4.4.5 total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begins. adlsmp is used to select between short and long sample times.when sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. the 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 111 result of the conversion is transferred to adcrh and adcrl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (adlsmp=0). if the bus frequency is less than 1/11th of the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for different conditions is summarized in table 8-12 . the maximum total conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is selectable by the adiclk bits, and the divide ratio is speci?d by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, then the conversion time for a single conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet adc speci?ations. table 8-12. total conversion time vs. control conditions conversion type adiclk adlsmp max total conversion time single or ?st continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or ?st continuous 10-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or ?st continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or ?st continuous 10-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles subsequent continuous 10-bit; f bus > f adck /11 xx 1 40 adck cycles 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 s x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 s 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 112 freescale semiconductor 8.4.5 automatic compare function the compare function can be con?ured to check for either an upper limit or lower limit. after the input is sampled and converted, the result is added to the two s complement of the compare value (adccvh and adccvl). when comparing to an upper limit (acfgt = 1), if the result is greater-than or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. the value generated by the addition of the conversion result and the two s complement of the compare value is transferred to adcrh and adcrl. upon completion of a conversion while the compare function is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result registers. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can be used to monitor the voltage on a channel while the mcu is in either wait or stop3 mode. the adc interrupt will wake the mcu when the compare condition is met. 8.4.6 mcu wait mode operation the wait instruction puts the mcu in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion clock source in wait is dependent on the de?ition of altclk for this mcu. consult the module introduction for information on altclk speci? to this mcu. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 8.4.7 mcu stop3 mode operation the stop instruction is used to put the mcu in a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 8.4.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of adcrh and adcrl are unaffected by stop3 mode.after exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 113 8.4.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc continues operation during stop3 mode. for guaranteed adc operation, the mcu s voltage regulator must remain active during stop3 mode. consult the module introduction for con?uration information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it continues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note it is possible for the adc module to wake the system from low power stop and cause the mcu to begin consuming run-level currents without generating a system level interrupt. to prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in section 8.4.4.2, ?ompleting conversions ) is cleared when entering stop3 and continuing adc conversions. 8.4.8 mcu stop1 and stop2 mode operation the adc module is automatically disabled when the mcu enters either stop1 or stop2 mode. all module registers contain their reset values following exit from stop1 or stop2. therefore the module must be re-enabled and re-con?ured following exit from stop1 or stop2. 8.5 initialization information this section gives an example which provides some basic direction on how a user would initialize and con?ure the adc module. the user has the ?xibility of choosing between con?uring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. refer to table 8-6 , table 8-7 , and table 8-8 for information used in this example. note hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 8.5.1 adc module initialization example 8.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the con?uration register (adccfg) to select the input clock source and the divide ratio used to generate the internal clock, adck. this register is also used for selecting sample time and low-power con?uration. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 114 freescale semiconductor 2. update status and control register 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control register 1 (adcsc1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. the input channel on which conversions will be performed is also selected here. 8.5.1.2 pseudo ?code example in this example, the adc module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal adck clock will be derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low power (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus clock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 unimplemented or reserved, always reads zero bit 1:0 00 reserved for freescale? internal use; always write zero adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (continuous conversions disabled) bit 4:0 adch 00001 input channel 1 selected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 115 figure 8-14. initialization flowchart for example 8.6 application information this section contains information for using the adc module in applications. the adc has been designed to be integrated into a microcontroller for use in embedded control applications requiring an a/d converter. 8.6.1 external pins and routing the following sections discuss the external pins associated with the adc module and how they should be used for best results. 8.6.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) which are available as separate pins on some devices. on other devices, v ssad is shared on the same pin as the mcu digital v ss , and on others, both v ssad and v ddad are shared with the mcu digital supply pins. in these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to the same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. yes no reset initialize adc adccfg = $98 adcsc1 = $41 adcsc2 = $00 check coco=1? read adcrh then adcrl to clear coco bit continue 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 116 freescale semiconductor in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 8.6.1.2 analog reference pins in addition to the analog supplies, the adc module has connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source that is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad . both v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current demand is a 0.1 f capacitor with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as near as possible to the package pins. resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. inductance in this path must be minimum (parasitic only). 8.6.1.3 analog input pins the external analog inputs are typically shared with digital i/o pins on mcu devices. the pin i/o control is disabled by setting the appropriate control bit in one of the pin control registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog input. this avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. also, the input buffer draws dc current when its input is not at either v dd or v ss . setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. use of 0.01 f capacitors with good high-frequency characteristics is suf?ient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to $3ff (full scale 10-bit representation) or $ff (full scale 8-bit representation). if the input is equal to or less than v refl , the converter circuit converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. there will be a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cycles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 117 8.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 8.6.2.1 sampling error for proper conversions, the input must be sampled long enough to achieve the proper accuracy. given the maximum input resistance of approximately 7k ? and input capacitance of approximately 5.5 pf, sampling to within 1/4 lsb (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the resistance of the external analog source (r as ) is kept below 5 k ? . higher source resistances or higher-accuracy sampling is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 8.6.2.2 pin leakage error leakage on the i/o pins can cause conversion error if the external analog source resistance (r as ) is high. if this error cannot be tolerated by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bit mode or 10 in 10-bit mode). 8.6.2.3 noise-induced errors system noise which occurs during the sample or conversion process can affect the accuracy of the conversion. the adc accuracy numbers are guaranteed as speci?d only if the following conditions are met: there is a 0.1 f low-esr capacitor from v refh to v refl . there is a 0.1 f low-esr capacitor from v ddad to v ssad . if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ? ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. for software triggered conversions, immediately follow the write to the adcsc1 with a wait instruction or stop instruction. for stop3 mode operation, select adack as the clock source. operation in stop3 reduces v dd noise but increases effective conversion time due to stop recovery. there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where external system activity causes radiated or conducted noise emissions or excessive v dd noise is coupled into the adc. in these situations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this will improve noise issues but will affect sample rate based on the external analog source resistance). 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 118 freescale semiconductor average the result by converting the analog input many times in succession and dividing the sum of the results. four samples are required to eliminate the effect of a 1 lsb , one-time error. reduce the effect of synchronous noise by operating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 8.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). each step ideally has the same height (1 code) and width. the width is de?ed as the delta between the transition points to one code and the next. the ideal code width for an n bit converter (in this case n can be 8 or 10), de?ed as 1 lsb , is: 1 lsb = (v refh - v refl ) / 2 n eqn. 8-2 there is an inherent quantization error due to the digitization of the result. for 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the ?st ($000) conversion is only 1/2 lsb and the code width of the last ($ff or $3ff) is 1.5 lsb . 8.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. these errors are: zero-scale error (e zs ) (sometimes called offset) this error is de?ed as the difference between the actual code width of the ?st conversion and the ideal code width (1/2 lsb ). note, if the ?st conversion is $001, then the difference between the actual $001 code width and its ideal (1 lsb )is used. full-scale error (e fs ) ?this error is de?ed as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb ). note, if the last conversion is $3fe, then the difference between the actual $3fe code width and its ideal (1 lsb ) is used. differential non-linearity (dnl) this error is de?ed as the worst-case difference between the actual code width and the ideal code width for all conversions. integral non-linearity (inl) this error is de?ed as the highest-value the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. total unadjusted error (tue) this error is de?ed as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 8.6.2.6 code jitter, non-monotonicity and missing codes analog-to-digital converters are susceptible to three special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is in?itesimally smaller than the transition voltage, the 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 119 converter yields the lower code (and vice-versa). however, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. this range is normally around 1/2 lsb and will increase with noise. this error may be reduced by repeatedly sampling the input and averaging the result. additionally the techniques discussed in section 8.6.2.3 will reduce this error. non-monotonicity is de?ed as when, except for code jitter, the converter converts to a lower code for a higher input voltage. missing codes are those values which are never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and to have no missing codes. 4 datasheet u .com analog-to-digital converter (s08adc10v1) MC9S08QD4 data sheet, rev. 1 120 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 121 chapter 9 internal clock source (s08icsv1) 9.1 introduction the internal clock source (ics) module provides clock source choices for the mcu. the module contains a frequency-locked loop (fll) as a clock source that is controllable by an internal reference clock. the module can provide this fll clock or the internal reference clock as a source for the mcu system clock, icsout. whichever clock source is chosen, icsout is passed through a bus clock divider (bdiv) which allows a lower ?al output clock frequency to be derived. icsout is two times the bus frequency. figure 9-1 shows the MC9S08QD4 with the ics module highlighted. 9.1.1 ics con?uration information bit-1 and bit-2 of ics control register 1 (icsc1) always read as 1. 4 datasheet u .com chapter 9 internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 122 freescale semiconductor figure 9-1. MC9S08QD4 block diagram highlighting ics block notes: 1 port pins are software con?urable with pullup device if input port. 2 port pins are software con?urable for output drive strength. 3 port pins are software con?urable for output slew rate control. 4 irq contains a software con?urable (irqpdd) pullup/pulldown device if pta5 enabled as irq pin function (irqpe = 1). 5 reset contains integrated pullup device if pta5 enabled as reset pin function (rstpe = 1). 6 pta5 does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 7 pta4 contains integrated pullup device if bkgd enabled (bkgdpe = 1). 8 when pin functions as kbi (kbipen = 1) and associated pin is con?ured to enable the pullup device, kbedgn can be used to recon?ure the pullup as a pulldown device. user ram hcs08 core cpu bdc 2-ch 16-bit timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management rti cop irq lvd voltage regulator port a pta5/tpm2ch0i/irq/ reset pta4/tpm2ch0o/bkgd/ms pta3/kbi1p3/tclk2/adc1p3 pta2/kbi1p2/tclk1/adc1p2 pta1/kbi1p1/tpm1ch1/adc1p1 pta0/kbi1p0/tpm1ch0/adc1p0 4-bit keyboard interrupt module (kbi) 256 bytes 16-mhz internal clock source (ics) v ss v dd v ssa v dda v refl v refh 4 analog-to-digital converter (adc) 10-bit tpm1ch0 tpm1ch1 bkgd/ms irq 4 1-ch 16-bit timer/pwm module (tpm2) tpm2ch0 user flash 4096 bytes tclk2 tclk1 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 123 9.1.2 features key features of the ics module are: frequency-locked loop (fll) is trimmable for accuracy 0.2% resolution using internal 32-khz reference 2% deviation over voltage and temperature using internal 32-khz reference 3 bit select for reference divider is provided internal reference clock has 9 trim bits available internal reference clock can be selected as the clock source for the mcu whichever clock is selected as the source can be divided down 2 bit select for clock divider is provided allowable dividers are: 1, 2, 4, 8 bdc clock is provided as a constant divide by 2 of the dco output fll engaged internal mode is automatically selected out of reset 9.1.3 modes of operation the ics features the following modes of operation: fei, fbi, fbilp, and stop. 9.1.3.1 fll engaged interna l (fei) in fll engaged internal mode, which is the default mode, the ics supplies a clock derived from the fll which is controlled by the internal reference clock. the bdc clock is supplied from the fll. 9.1.3.2 fll bypassed interna l (fbi) in fll bypassed internal mode, the fll is enabled and controlled by the internal reference clock, but is bypassed. the ics supplies a clock derived from the internal reference clock. the bdc clock is supplied from the fll. 9.1.3.3 fll bypassed interna l low power (fbilp) in fll bypassed internal low power mode, the fll is disabled and bypassed, and the ics supplies a clock derived from the internal reference clock. the bdc clock is not available. 9.1.3.4 stop (stop) in stop mode, the fll is disabled and the external reference clock can be selected to be enabled or disabled. the bdc clock is not available. ics does not provide an mcu clock source. 9.1.4 block diagram this section contains the ics block diagram. 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 124 freescale semiconductor figure 9-2. internal clock source (ics) block diagram 9.2 external signal description no ics signal connects off chip. 9.3 register de?ition 9.3.1 ics control register 1 (icsc1) 7 654 3 210 r0 clks 00 0 11 irefsten w reset: 0 0 0 0 0 1 1 0 figure 9-3. ics control register 1 (icsc1) table 9-1. ics control register 1 field descriptions field description 6 clks clock source select ?selects the clock source that controls the bus frequency. the actual bus frequency depends on the value of the bdiv bits. 0 output of fll is selected. 1 internal reference clock is selected. 0 irefsten internal reference stop enable ?the irefsten bit controls whether or not the internal reference clock remains enabled when the ics enters stop mode. 1 internal reference clock stays enabled in stop if irclken is set or if ics is in fei, fbi, or fbilp mode before entering stop 0 internal reference clock is disabled in stop dco filter trim 9 clks n=0-3 / 2 n internal reference clock bdiv 9 icsout 1 icsirclk irefsten lp icsffclk dcoout fll (32 khz) 1 icsout is two times the bus frequency icsirclk /2 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 125 9.3.2 ics control register 2 (icsc2) 9.3.3 ics trim register (icstrm) 76543210 r bdiv 00 lp 00 0 w reset: 0 1 0 0 0 0 0 0 figure 9-4. ics control register 2 (icsc2) table 9-2. ics control register 2 field descriptions field description 7:6 bdiv bus frequency divider selects the amount to divide down the clock source selected by the clks bits. this controls the bus frequency. 00 encoding 0 ?divides selected clock by 1 01 encoding 1 ?divides selected clock by 2 (reset default) 10 encoding 2 ?divides selected clock by 4 11 encoding 3 ?divides selected clock by 8 3 lp low power select ?the lp bit controls whether the fll is disabled in fll bypassed modes. 1 fll is disabled in bypass modes unless bdm is active 0 fll is not disabled in bypass mode 7 654 3 210 r trim w por: 1 0 0 0 0 0 0 0 reset: u u u u u u u u figure 9-5. ics trim register (icstrm) table 9-3. ics trim register field descriptions field description 7:0 trim ics trim setting ?the trim bits control the internal reference clock frequency by controlling the internal reference clock period. the bits?effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). increasing the binary value in trim will increase the period, and decreasing the value will decrease the period. an additional ?e trim bit is available in icssc as the ftrim bit. 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 126 freescale semiconductor 9.3.4 ics status and control (icssc) 9.4 functional description 9.4.1 operational modes the states of the ics are shown as a state diagram and are described in the following sections. the arrows indicate the allowed movements between the states. figure 9-7. clock switching modes 7 654 3 210 r 0 0 0 0 0 clkst 0 ftrim w por: reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u figure 9-6. ics status and control register (icssc) table 9-4. ics status and control register field descriptions field description 2 clkst clock mode status ?the clkst bit indicate the current clock mode. the clkst bit doesn? update immediately after a write to the clks bits due to internal synchronization between clock domains. 0 output of fll is selected. 1 fll bypassed, internal reference clock is selected. ftrim 0 ics fine trim ?the ftrim bit controls the smallest adjustment of the internal reference clock frequency. setting ftrim will increase the period and clearing ftrim will decrease the period by the smallest amount possible. fll bypassed internal low power(fbilp) clks=0 1 ics enters its stop state when mcu enters stop, fll is always disabled. ics returns to the state that was active before mcu entered stop, unless a reset occurs while in stop. 2 if irefsten is set when mcu enters stop, the icsirclk remains running. fll engaged internal (fei) fll bypassed internal (fbi) clks=1 lp=0 clks=1 lp=1 stop 1, 2 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 127 9.4.1.1 fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation out of any reset and is entered when clks is written to 0 in fll engaged internal mode, the icsout clock is derived from the fll clock, which is controlled by the internal reference clock. the fll loop will lock the frequency to 512 times the ?ter frequency. 9.4.1.2 fll bypassed internal (fbi) the fll bypassed internal (fbi) mode is entered when clks is written to 1 and lp bit is written to 0. in fll bypassed internal mode, the icsout clock is derived from the internal reference clock. the fll clock is controlled by the internal reference clock, and the fll loop will lock the fll frequency to 512 times the ?ter frequency, as selected by the rdiv bits. the icslclk will be available for bdc communications, and the internal reference clock is enabled. 9.4.1.3 fll bypassed internal low power (fbilp) the fll bypassed internal low power (fbilp) mode is entered when clks bits are written to 1and lp bit is written to 1. in fll bypassed internal low power mode, the icsout clock is derived from the internal reference clock and the fll is disabled. 9.4.1.4 stop ics stop mode is entered whenever the mcu enters stop. in this mode, all ics clock signals are stopped except icsirclk, which will be active in stop mode when irefsten bit is written to 1. when the mcu is interrupted from stop, the ics will go back to the operating mode that was running when the mcu entered stop. if the internal reference was not running in stop (irefsten = 0), the ics will take some time, t ir_wu , for the internal reference to wake up. if the internal reference was already running in stop (irefsten = 1), entering into fei will take some time, t ?_wu , for the fll to return its previously acquired frequency. 9.4.2 mode switching when changing from fbilp to either fei or fbi, or anytime the trim value is written, the user should wait the fll acquisition time, t acquire , before fll will be guranteed to be at desired frequency. 9.4.3 bus frequency divider the bdiv bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 4 datasheet u .com internal clock source (s08icsv1) MC9S08QD4 data sheet, rev. 1 128 freescale semiconductor 9.4.4 low power bit usage the low power bit (lp) is provided to allow the fll to be disabled and thus conserve power when it is not being used. however, in some applications it may be desirable to enable the fll and allow it to lock for maximum accuracy before switching to an fll engaged mode. do this by writing the lp bit to 0. 9.4.5 internal reference clock the icsirclk frequency can be re-targeted by trimming the period of the internal reference clock. this can be done by writing a new value to the trim bits in the icstrm register. writing a larger value will slow down the icsirclk frequency, and writing a smaller value to the icstrm register will speed up the icsirclk frequency. the trim bits will effect the icsout frequency if the ics is in fll engaged internal (fei), fll bypassed internal (fbi), or fll bypassed internal low power (fbilp) mode. the trim and ftrim value will not be affected by a reset. if irefsten is set , the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. all mcu devices are factory programmed with a trim value in a reserved memory location. this value can be copied to the icstrm register during reset initialization. the factory trim value does not include the ftrim bit. for ?er precision, the user can trim the internal oscillator in the application and set the ftrim bit accordingly. 9.4.6 fixed frequency clock the ics provides the icsffclk output, which can be used as an additional clock source to a peripheral, such as a timer, when the icsis in fei. icsffclk is not a valid clock source for a peripheral when in fbi or fbilp modes. icsffclk is icsrclk divided by two. 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 129 chapter 10 keyboard interrupt (s08kbiv2) 10.1 introduction the keyboard interrupt kbi module provides up to eight independently enabled external interrupt sources. only four (kbi1p0?bi1p3) of the possible interrupts are implemented on the MC9S08QD4 mcu. these inputs are selected by the kbipe bits. figure 10-1 shows the MC9S08QD4 with the kbi module and pins highlighted. 4 datasheet u .com chapter 10 keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 130 freescale semiconductor figure 10-1. MC9S08QD4 block diagram highlighting kbi block and pins notes: 1 port pins are software con?urable with pullup device if input port. 2 port pins are software con?urable for output drive strength. 3 port pins are software con?urable for output slew rate control. 4 irq contains a software con?urable (irqpdd) pullup/pulldown device if pta5 enabled as irq pin function (irqpe = 1). 5 reset contains integrated pullup device if pta5 enabled as reset pin function (rstpe = 1). 6 pta5 does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 7 pta4 contains integrated pullup device if bkgd enabled (bkgdpe = 1). 8 when pin functions as kbi (kbipen = 1) and associated pin is con?ured to enable the pullup device, kbedgn can be used to recon?ure the pullup as a pulldown device. user ram hcs08 core cpu bdc 2-ch 16-bit timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management rti cop irq lvd voltage regulator port a pta5/tpm2ch0i/irq/ reset pta4/tpm2ch0o/bkgd/ms pta3/kbi1p3/tclk2/adc1p3 pta2/kbi1p2/tclk1/adc1p2 pta1/kbi1p1/tpm1ch1/adc1p1 pta0/kbi1p0/tpm1ch0/adc1p0 4-bit keyboard interrupt module (kbi) 256 bytes 16-mhz internal clock source (ics) v ss v dd v ssa v dda v refl v refh 4 analog-to-digital converter (adc) 10-bit tpm1ch0 tpm1ch1 bkgd/ms irq 4 1-ch 16-bit timer/pwm module (tpm2) tpm2ch0 user flash 4096 bytes tclk2 tclk1 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 131 10.1.1 features the kbi features include: up to eight keyboard interrupt pins with individual pin enable bits. each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. one software enabled keyboard interrupt. exit from low-power modes. 10.1.2 modes of operation this section de?es the kbi operation in wait, stop, and background debug modes. 10.1.2.1 kbi in wait mode the kbi continues to operate in wait mode if enabled before executing the wait instruction. therefore, an enabled kbi pin (kbpex = 1) can be used to bring the mcu out of wait mode if the kbi interrupt is enabled (kbie = 1). 10.1.2.2 kbi in stop modes the kbi operates asynchronously in stop3 mode if enabled before executing the stop instruction. therefore, an enabled kbi pin (kbpex = 1) can be used to bring the mcu out of stop3 mode if the kbi interrupt is enabled (kbie = 1). during either stop1 or stop2 mode, the kbi is disabled. in some systems, the pins associated with the kbi may be sources of wakeup from stop1 or stop2, see the stop modes section in the modes of operation chapter. upon wake-up from stop1 or stop2 mode, the kbi module will be in the reset state. 10.1.2.3 kbi in active background mode when the microcontroller is in active background mode, the kbi will continue to operate normally. 10.1.3 block diagram the block diagram for the keyboard interrupt module is shown figure 10-2 . 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 132 freescale semiconductor figure 10-2. keyboard interrupt (kbi) block diagram 10.2 external signal description the kbi input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. the kbi input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. the signal properties of kbi are shown in table 10-1 . table 10-1. signal properties signal function i/o kbipn keyboard interrupt pins i dq ck clr v dd kbmod kbie keyboard interrupt ff kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 0 1 s kbedg0 kbi p0 kbi pn kbi interrupt reques t 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 133 10.3 register de?ition the kbi includes three registers: an 8-bit pin status and control register. an 8-bit pin enable register. an 8-bit edge select register. refer to the direct-page register summary in the memory chapter for the absolute address assignments for all kbi registers. this section refers to registers and control bits only by their names and relative address offsets. some mcus may have more than one kbi, so register names include placeholder characters to identify which kbi is being referenced. 10.3.1 kbi status and control register ( kbi sc) kbisc contains the status ?g and control bits, which are used to con?ure the kbi. 10.3.2 kbi pin enable register (kbipe) kbipe contains the pin enable control bits. 7 6 5 4 3 2 1 0 r 0 0 0 0 kbf 0 kbie kbmod w kback reset: 0 0 0 0 0 0 0 0 = unimplemented figure 10-3. kbi status and control register table 10-2. kbisc register field descriptions field description 7:4 unused register bits, always read 0. 3 kbf keyboard interrupt flag ?kbf indicates when a keyboard interrupt is detected. writes have no effect on kbf. 0 no keyboard interrupt detected. 1 keyboard interrupt detected. 2 kback keyboard acknowledge ?writing a 1 to kback is part of the ?g clearing mechanism. kback always reads as 0. 1 kbie keyboard interrupt enable ?kbie determines whether a keyboard interrupt is requested. 0 keyboard interrupt request not enabled. 1 keyboard interrupt request enabled. 0 kbmod keyboard detection mode ?kbmod (along with the kbedg bits) controls the detection mode of the keyboard interrupt pins.0keyboard detects edges only. 1 keyboard detects both edges and levels. 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 134 freescale semiconductor 10.3.3 kbi edge select register (kbies) kbies contains the edge select control bits. 10.4 functional description this on-chip peripheral module is called a keyboard interrupt (kbi) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. however, these inputs are also useful as extra external interrupt inputs and as an external means of waking the mcu from stop or wait low-power modes. the kbi module allows up to eight pins to act as additional interrupt sources. writing to the kbipen bits in the keyboard interrupt pin enable register (kbipe) independently enables or disables each kbi pin. each kbi pin can be con?ured as edge sensitive or edge and level sensitive based on the kbmod bit in the keyboard interrupt status and control register (kbisc). edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. the polarity of the edge or edge and level sensitivity is selected using the kbedgn bits in the keyboard interrupt edge select register (kbies). 7 6 5 4 3 2 1 0 r kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 w reset: 0 0 0 0 0 0 0 0 figure 10-4. kbi pin enable register table 10-3. kbipe register field descriptions field description 7:0 kbipen keyboard pin enables ?each of the kbipen bits enable the corresponding keyboard interrupt pin. 0 pin not enabled as keyboard interrupt. 1 pin enabled as keyboard interrupt. 7 6 5 4 3 2 1 0 r kbedg7 kbedg6 kbedg5 kbedg4 kbedg3 kbedg2 kbedg1 kbedg0 w reset: 0 0 0 0 0 0 0 0 figure 10-5. kbi edge select register table 10-4. kbies register field descriptions field description 7:0 kbedgn keyboard edge selects ?each of the kbedgn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 falling edge/low level. 1 rising edge/high level. 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 135 synchronous logic is used to detect edges. prior to detecting an edge, enabled keyboard inputs must be at the deasserted logic level. a falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 10.4.1 edge only sensitivity a valid edge on an enabled kbi pin will set kbf in kbisc. if kbie in kbisc is set, an interrupt request will be presented to the cpu. clearing of kbf is accomplished by writing a 1 to kback in kbisc. 10.4.2 edge and level sensitivity a valid edge or level on an enabled kbi pin will set kbf in kbisc. if kbie in kbisc is set, an interrupt request will be presented to the cpu. clearing of kbf is accomplished by writing a 1 to kback in kbisc provided all enabled keyboard inputs are at their deasserted levels. kbf will remain set if any enabled kbi pin is asserted while attempting to clear by writing a 1 to kback. 10.4.3 kbi pullup/pulldown resistors the kbi pins can be con?ured to use an internal pullup/pulldown resistor using the associated i/o port pullup enable register. if an internal resistor is enabled, the kbies register is used to select whether the resistor is a pullup (kbedgn = 0) or a pulldown (kbedgn = 1). 10.4.4 kbi initialization when a keyboard interrupt pin is ?st enabled it is possible to get a false keyboard interrupt ?g. to prevent a false interrupt request during keyboard initialization, the user should do the following: 1. mask keyboard interrupts by clearing kbie in kbisc. 2. enable the kbi polarity by setting the appropriate kbedgn bits in kbies. 3. if using internal pullup/pulldown device, con?ure the associated pullup enable bits in ptxpe. 4. enable the kbi pins by setting the appropriate kbipen bits in kbipe. 5. write to kback in kbisc to clear any false interrupts. 6. set kbie in kbisc to enable interrupts. 4 datasheet u .com keyboard interrupt (s08kbiv2) MC9S08QD4 data sheet, rev. 1 136 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 137 chapter 11 timer/pulse-width modulator (s08tpmv2) 11.1 introduction figure 11-1 shows the MC9S08QD4 block diagram with the tpm module and pins highlighted. 11.1.1 tpm2 con?uration information the tpm2 module consist of a single channel, tpm2ch0, that is multiplexed with input pin pta4 and output pin pta5. when tpm2 is con?ured for input capture, the tpm2ch0 will connect to the pta5 (tpm2ch0i). when tpm2 is con?ured for output compare, the tpm2ch0 will connect to the pta4 (tpm2ch0o). when tpm2 is disabled, pta4 and pta5 function as standard port pins. 11.1.2 tclk1 and tclk2 con?uration information the tclk1 and tclk2 are the external clock source inputs for tpm1 and tpm2 respectively. 4 datasheet u .com chapter 11 timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 138 freescale semiconductor figure 11-1. MC9S08QD4 block diagram highlighting tpm block and pins notes: 1 port pins are software con?urable with pullup device if input port. 2 port pins are software con?urable for output drive strength. 3 port pins are software con?urable for output slew rate control. 4 irq contains a software con?urable (irqpdd) pullup/pulldown device if pta5 enabled as irq pin function (irqpe = 1). 5 reset contains integrated pullup device if pta5 enabled as reset pin function (rstpe = 1). 6 pta5 does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pullup is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 7 pta4 contains integrated pullup device if bkgd enabled (bkgdpe = 1). 8 when pin functions as kbi (kbipen = 1) and associated pin is con?ured to enable the pullup device, kbedgn can be used to recon?ure the pullup as a pulldown device. user ram hcs08 core cpu bdc 2-ch 16-bit timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management rti cop irq lvd voltage regulator port a pta5/tpm2ch0i/irq/ reset pta4/tpm2ch0o/bkgd/ms pta3/kbi1p3/tclk2/adc1p3 pta2/kbi1p2/tclk1/adc1p2 pta1/kbi1p1/tpm1ch1/adc1p1 pta0/kbi1p0/tpm1ch0/adc1p0 4-bit keyboard interrupt module (kbi) 256 bytes 16-mhz internal clock source (ics) v ss v dd v ssa v dda v refl v refh 4 analog-to-digital converter (adc) 10-bit tpm1ch0 tpm1ch1 bkgd/ms irq 4 1-ch 16-bit timer/pwm module (tpm2) tpm2ch0 user flash 4096 bytes tclk2 tclk1 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 139 11.1.3 features the tpm has the following features: each tpm may be con?ured for buffered, center-aligned pulse-width modulation (cpwm) on all channels clock sources independently selectable per tpm (multiple tpms device) selectable clock sources (device dependent): bus clock, ?ed system clock, external pin clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 16-bit free-running or up/down (cpwm) count operation 16-bit modulus register to control counter range timer system enable one interrupt per channel plus a terminal count interrupt for each tpm module (multiple tpms device) channel features: each channel may be input capture, output compare, or buffered edge-aligned pwm rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action selectable polarity on pwm outputs 11.1.4 block diagram figure 11-2 shows the structure of a tpm. some mcus include more than one tpm, with various numbers of channels. 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 140 freescale semiconductor figure 11-2. tpm block diagram the central component of the tpm is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the tpm is con?ured for center-aligned pwm. the tpm counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned pwm functions. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter. (the values 0x0000 or 0xffff effectively make the counter free running.) software can read the counter value at any time without affecting the counting sequence. any write to either byte of the tpmxcnt counter resets the counter regardless of the data value written. prescale and select 16-bit comparator main 16-bit counter 16-bit comparator 16-bit latch port 16-bit comparator 16-bit latch channel 0 channel 1 internal bus logic interrupt port logic 16-bit comparator 16-bit latch channel n port logic counter reset divide by clock source off, bus, xclk, ext busclk xclk select sync interrupt interrupt interrupt 1, 2, 4, 8, 16, 32, 64, or 128 logic logic logic logic clksa clksb ps2 ps1 ps0 cpwms toie tof els0a ch0f els0b els1b els1a elsnb elsna ch1f chnf ch0ie ch1ie chnie ms1b ms0b msnb ms0a ms1a msna . . . . . . . . . tpmx modh: tpmx modl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxcnvh:tpmxcnvl tpmxchn tpmxch1 tpmxch0 tpmxclk 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 141 all tpm channels are programmable independently as input capture, output compare, or buffered edge-aligned pwm channels. 11.2 external signal description when any pin associated with the timer is con?ured as a timer input, a passive pullup can be enabled. after reset, the tpm modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 11.2.1 external tpm clock sources when control bits clksb:clksa in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for tpmx are driven by an external clock source, tpmxclk, connected to an i/o pin. a synchronizer is needed between the external clock and the rest of the tpm. this synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. the upper frequency limit for this external clock source is speci?d to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (pll) or frequency-locked loop (fll) frequency jitter effects. on some devices the external clock input is shared with one of the tpm channels. when a tpm channel is shared as the external clock input, the associated tpm channel cannot use the pin. (the channel can still be used in output compare mode as a software timer.) also, if one of the tpm channels is used as the external clock input, the corresponding elsnb:elsna control bits must be set to 0:0 so the channel is not trying to use the same pin. 11.2.2 tpmxchn ?tpmx channel n i/o pins each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the con?uration of the channel. in some cases, no pin function is needed so the pin reverts to being controlled by general-purpose i/o controls. when a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). see the pins and connections chapter for additional information about shared pin functions. 11.3 register de?ition the tpm includes: an 8-bit status and control register (tpmxsc) a 16-bit counter (tpmxcnth:tpmxcntl) a 16-bit modulo register (tpmxmodh:tpmxmodl) each timer channel has: an 8-bit status and control register (tpmxcnsc) a 16-bit channel value register (tpmxcnvh:tpmxcnvl) refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all tpm registers. this section refers to registers and control bits only by their names. a 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 142 freescale semiconductor freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 11.3.1 timer status and control register (tpmxsc) tpmxsc contains the over?w status ?g and control bits that are used to con?ure the interrupt enable, tpm con?uration, clock source, and prescale divisor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w reset 00000000 = unimplemented or reserved figure 11-3. timer status and control register (tpmxsc) table 11-1. tpmxsc register field descriptions field description 7 tof timer over?w flag ?this ?g is set when the tpm counter changes to 0x0000 after reaching the modulo value programmed in the tpm counter modulo registers. when the tpm is con?ured for cpwm, tof is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. clear tof by reading the tpm status and control register when tof is set and then writing a 0 to tof. if another tpm over?w occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. reset clears tof. writing a 1 to tof has no effect. 0 tpm counter has not reached modulo value or over?w 1 tpm counter has over?wed 6 toie timer over?w interrupt enable ?this read/write bit enables tpm over?w interrupts. if toie is set, an interrupt is generated when tof equals 1. reset clears toie. 0 tof interrupts inhibited (use software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select this read/write bit selects cpwm operating mode. reset clears this bit so the tpm operates in up-counting mode for input capture, output compare, and edge-aligned pwm functions. setting cpwms recon?ures the tpm to operate in up-/down-counting mode for cpwm functions. reset clears cpwms. 0 all tpmx channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channel s status and control register 1 all tpmx channels operate in center-aligned pwm mode 4:3 clks[b:a] clock source select as shown in table 11-2 , this 2-bit ?ld is used to disable the tpm system or select one of three clock sources to drive the counter prescaler. the external source and the xclk are synchronized to the bus clock by an on-chip synchronization circuit. 2:0 ps[2:0] prescale divisor select ?this 3-bit ?ld selects one of eight divisors for the tpm clock input as shown in table 11-3 . this prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the tpm system. 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 143 11.3.2 timer counter registers (tpmxcnth:tpmxcntl) the two read-only tpm counter registers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this allows coherent 16-bit reads in either order. the coherency mechanism is automatically restarted by an mcu reset, a write of any value to tpmxcnth or tpmxcntl, or any write to the timer status/control register (tpmxsc). reset clears the tpm counter registers. table 11-2. tpm clock source selection clksb:clksa tpm clock source to prescaler input 0:0 no clock selected (tpmx disabled) 0:1 bus rate clock (busclk) 1:0 fixed system clock (xclk) 1:1 external source (tpmxclk) 1,2 1 the maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 if the external clock input is shared with channel n and is selected as the tpm clock source, the corresponding elsnb:elsna control bits should be set to 0:0 so channel n does not try to use the same pin for a con?cting function. table 11-3. prescale divisor selection ps2:ps1:ps0 tpm clock source divided-by 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter. reset 00000000 figure 11-4. timer counter register high (tpmxcnth) 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 144 freescale semiconductor when background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 11.3.3 timer counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock (cpwms = 0) or starts counting down (cpwms = 1), and the over?w ?g (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits tof and over?w interrupts until the other byte is written. reset sets the tpm counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled). it is good practice to wait for an over?w interrupt so both bytes of the modulo register can be written well before a new over?w. an alternative approach is to reset the tpm counter before writing to the tpm modulo registers to avoid confusion about when the ?st counter over?w will occur. 76543210 r bit 7 654321 bit 0 w any write to tpmxcntl clears the 16-bit counter. reset 00000000 figure 11-5. timer counter register low (tpmxcntl) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 11-6. timer counter modulo register high (tpmxmodh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 11-7. timer counter modulo register low (tpmxmodl) 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 145 11.3.4 timer channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel interrupt status ?g and control bits that are used to con?ure the interrupt enable, channel con?uration, and pin function. 76543210 r chnf chnie msnb msna elsnb elsna 00 w reset 00000000 = unimplemented or reserved figure 11-8. timer channel n status and control register (tpmxcnsc) table 11-4. tpmxcnsc register field descriptions field description 7 chnf channel n flag when channel n is con?ured for input capture, this ?g bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. this ?g is seldom used with center-aligned pwms because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf would remain set after the clear sequence was completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost by clearing a previous chnf. reset clears chnf. writing a 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event occurred on channel n 6 chnie channel n interrupt enable ?this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n ?when cpwms = 0, msnb = 1 con?ures tpm channel n for edge-aligned pwm mode. for a summary of channel mode and setup controls, refer to table 11-5 . 4 msna mode select a for tpm channel n when cpwms = 0 and msnb = 0, msna con?ures tpm channel n for input capture mode or output compare mode. refer to table 11-5 for a summary of channel mode and setup controls. 3:2 elsn[b:a] edge/level select bits ?depending on the operating mode for the timer channel as set by cpwms:msnb:msna and shown in table 11-5 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 con?ures the related timer pin as a general-purpose i/o pin unrelated to any timer channel functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 146 freescale semiconductor if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. typically, a program would clear status ?gs after changing channel con?uration bits and before enabling channel interrupts or using the status ?gs to avoid any unexpected behavior. 11.3.5 timer channel value registers (tpmxcnvh:tpmxcnvl) these read/write registers contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the channel value registers are cleared by reset. in input capture mode, reading either byte (tpmxcnvh or tpmxcnvl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this latching mechanism also resets (becomes unlatched) when the tpmxcnsc register is written. table 11-5. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode con?uration x xx 00 pin not used for tpm channel; use as an external clock for the tpm or revert to general-purpose i/o 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 00 output compare software compare only 01 toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 11-9. timer channel value register high (tpmxcnvh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 11-10. timer channel value register low (tpmxcnvl) 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 147 in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. this latching mechanism may be manually reset by writing to the tpmxcnsc register. this latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 11.4 functional description all tpm functions are associated with a main 16-bit counter that allows ?xible selection of the clock source and prescale divisor. a 16-bit modulo register also is associated with the main 16-bit counter in the tpm. each tpm channel is optionally associated with an mcu pin and a maskable interrupt function. the tpm has center-aligned pwm capabilities controlled by the cpwms control bit in tpmxsc. when cpwms is set to 1, timer counter tpmxcnt changes to an up-/down-counter and all channels in the associated tpm act as center-aligned pwm channels. when cpwms = 0, each channel can independently be con?ured to operate in input capture, output compare, or buffered edge-aligned pwm mode. the following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 11.4.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count over?w, and manual counter reset. after any mcu reset, clksb:clksa = 0:0 so no clock source is selected and the tpm is inactive. normally, clksb:clksa would be set to 0:1 so the bus clock drives the timer counter. the clock source for the tpm can be selected to be off, the bus clock (busclk), the ?ed system clock (xclk), or an external input. the maximum frequency allowed for the external clock option is one-fourth the bus rate. refer to section 11.3.1, ?imer status and control register (tpmxsc) and table 11-2 for more information about clock source selection. when the microcontroller is in active background mode, the tpm temporarily suspends all counting until the microcontroller returns to normal user operating mode. during stop mode, all tpm clocks are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. the main 16-bit counter has two counting modes. when center-aligned pwm is selected (cpwms = 1), the counter operates in up-/down-counting mode. otherwise, the counter operates as a simple up-counter. as an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 148 freescale semiconductor when center-aligned pwm operation is speci?d, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. both 0x0000 and the terminal count value (value in tpmxmodh:tpmxmodl) are normal length counts (one timer clock period long). an interrupt ?g and enable are associated with the main 16-bit counter. the timer over?w ?g (tof) is a software-accessible indication that the timer counter has over?wed. the enable signal selects between software polling (toie = 0) where no hardware interrupt is generated, or interrupt-driven operation (toie = 1) where a static hardware interrupt is automatically generated whenever the tof ?g is 1. the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the main 16-bit counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the main 16-bit counter is operating in up-/down-counting mode, the tof ?g gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the 0x0000 count value corresponds to the center of a period.) because the hcs08 mcu is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. whenever either byte of the counter is read (tpmxcnth or tpmxcntl), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the ?st byte was read. the counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. the main timer counter can be reset manually at any time by writing any value to either byte of the timer count tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 11.4.2 channel mode selection provided cpwms = 0 (center-aligned pwm operation is not speci?d), the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and buffered edge-aligned pwm. 11.4.2.1 input capture mode with the input capture function, the tpm can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tpm latches the contents of the tpm counter into the channel value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. when either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an input capture event sets a ?g bit (chnf) that can optionally generate a cpu interrupt request. 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 149 11.4.2.2 output compare mode with the output compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reaches the value in the channel value registers of an output compare channel, the tpm can set, clear, or toggle the channel pin. in output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. this coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an output compare event sets a ?g bit (chnf) that can optionally generate a cpu interrupt request. 11.4.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer counter (cpwms = 0) and can be used when other channels in the same tpm are con?ured for input capture or output compare functions. the period of this pwm signal is determined by the setting in the modulus register (tpmxmodh:tpmxmodl). the duty cycle is determined by the setting in the timer channel value register (tpmxcnvh:tpmxcnvl). the polarity of this pwm signal is determined by the setting in the elsna control bit. duty cycle cases of 0 percent and 100 percent are possible. as figure 11-11 shows, the output compare value in the tpm channel registers determines the pulse width (duty cycle) of the pwm signal. the time between the modulus over?w and the output compare is the pulse width. if elsna = 0, the counter over?w forces the pwm signal high and the output compare forces the pwm signal low. if elsna = 1, the counter over?w forces the pwm signal low and the output compare forces the pwm signal high. figure 11-11. pwm period and pulse width (elsna = 0) when the channel value register is set to 0x0000, the duty cycle is 0 percent. by setting the timer channel value register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting, 100% duty cycle can be achieved. this implies that the modulus setting must be less than 0xffff to get 100% duty cycle. because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to either register, tpmxcnvh or tpmxcnvl, write to buffer registers. in edge-pwm mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the tpmxcnth:tpmxcntl counter is 0x0000. (the new duty cycle does not take effect until the next full period.) period pulse width overflow overflow overflow output compare output compare output compare tpmxc 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 150 freescale semiconductor 11.4.3 center-aligned pwm mode this type of pwm output uses the up-/down-counting mode of the timer counter (cpwms = 1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal and the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) eqn. 11-1 period = 2 x (tpmxmodh:tpmxmodl); for tpmxmodh:tpmxmodl = 0x0001?x7fff eqn. 11-2 if the channel value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if generation of 100% duty cycle is not necessary). this is not a signi?ant limitation because the resulting period is much longer than required for normal applications. tpmxmodh:tpmxmodl = 0x0000 is a special case that should not be used with center-aligned pwm mode. when cpwms = 0, this case corresponds to the counter running free from 0x0000 through 0xffff, but when cpwms = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. figure 11-12 shows the output compare value in the tpm channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the cpwm signal. if elsna = 0, the compare match while counting up forces the cpwm output signal low and a compare match while counting down forces the output high. the counter counts up until it reaches the modulo setting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 11-12. cpwm period and pulse width (elsna = 0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also required for some types of motor drives. because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers, tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, actually write to buffer registers. values are period pulse width count = count = 0 output compare (count up) output compare (count down) count = tpmxmodh:tpmx tpm1c tpmxmodh:tpmx 2 x 2 x 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 freescale semiconductor 151 transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter over?ws (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). this tpmxcnt over?w requirement only applies to pwm channels, not output compares. optionally, when tpmxcnth:tpmxcntl = tpmxmodh:tpmxmodl, the tpm can generate a tof interrupt at the end of this count. the user can choose to reload any number of the pwm buffers, and they will all update simultaneously at the start of a new period. writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo registers. writing to tpmxcnsc cancels any values written to the channel value registers and resets the coherency mechanism for tpmxcnvh:tpmxcnvl. 11.5 tpm interrupts the tpm generates an optional interrupt for the main counter over?w and an interrupt for each channel. the meaning of channel interrupts depends on the mode of operation for each channel. if the channel is con?ured for input capture, the interrupt ?g is set each time the selected input capture edge is recognized. if the channel is con?ured for output compare or pwm modes, the interrupt ?g is set each time the main timer counter matches the value in the 16-bit channel value register. see the resets, interrupts, and system con?uration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. for each interrupt source in the tpm, a ?g bit is set on recognition of the interrupt condition such as timer over?w, channel input capture, or output compare events. this ?g may be read (polled) by software to verify that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt ?g equals 1. it is the responsibility of user software to perform a sequence of steps to clear the interrupt ?g before returning from the interrupt service routine. 11.5.1 clearing timer interrupt flags tpm interrupt ?gs are cleared by a 2-step process that includes a read of the ?g bit while it is set (1) followed by a write of 0 to the bit. if a new event is detected between these two steps, the sequence is reset and the interrupt ?g remains set after the second step to avoid the possibility of missing the new event. 11.5.2 timer over?w interrupt description the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the counter is operating in up-/down-counting mode, the tof ?g gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the 0x0000 count value corresponds to the center of a period.) 4 datasheet u .com timer/pulse-width modulator (s08tpmv2) MC9S08QD4 data sheet, rev. 1 152 freescale semiconductor 11.5.3 channel event interrupt description the meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned pwm, or center-aligned pwm). when a channel is con?ured as an input capture channel, the elsnb:elsna control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. when the selected edge is detected, the interrupt ?g is set. the ?g is cleared by the 2-step sequence described in section 11.5.1, ?learing timer interrupt flags . when a channel is con?ured as an output compare channel, the interrupt ?g is set each time the main timer counter matches the 16-bit value in the channel value register. the ?g is cleared by the 2-step sequence described in section 11.5.1, ?learing timer interrupt flags . 11.5.4 pwm end-of-duty-cycle events for channels that are con?ured for pwm operation, there are two possibilities: when the channel is con?ured for edge-aligned pwm, the channel ?g is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. when the channel is con?ured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel ?g is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. the ?g is cleared by the 2-step sequence described in section 11.5.1, ?learing timer interrupt flags . 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 153 chapter 12 development support 12.1 introduction development support systems in the hcs08 include the background debug controller (bdc). the bdc provides a single-wire debug interface to the target mcu that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoints, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through commands fed into the target mcu via the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. 12.1.1 module con?uration the alternative bdc clock source for MC9S08QD4 is the icgclk. see chapter 9, ?nternal clock source (s08icsv1) ?for more information about icgclk and how to select clock sources. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 154 freescale semiconductor 12.1.2 features features of the bdc module include: single pin for mode selection and background communications bdc registers are not located in the memory map sync command to determine target communications rate non-intrusive commands for memory access active background mode commands for cpu register access go and trace1 commands background command can wake cpu from stop or wait modes one hardware address breakpoint built into bdc oscillator runs in stop mode, if bdc enabled cop watchdog disabled while in active background mode 12.2 background debug controller (bdc) all mcus in the hcs08 family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands allow the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode. non-intrusive commands can be executed at any time even while the user s program is running. non-intrusive commands allow a user to read or write mcu memory locations or access status and control registers within the background debug controller. typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. depending on the development tool vendor, this interface pod may use a standard rs-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (usb) to communicate between the host pc and the pod. the pod typically connects to the target system with ground, the bkgd pin, reset, and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. sometimes v dd can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 155 figure 12-1. bdm tool connector 12.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communication of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the user s application program. this pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. bdc serial communications use a custom serial protocol ?st introduced on the m68hc12 family of microcontrollers. this protocol assumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most signi?ant bit ?st (msb ?st). for a detailed description of the communications protocol, refer to section 12.2.2, ?ommunication details . if a host is attempting to communicate with a target mcu that has an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync response signal from which the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. unlike typical open-drain pins, the external rc time constant on this pin, which is in?enced by external capacitance, plays almost no role in signal rise time. the custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level con?cts. refer to section 12.2.2, ?ommunication details , for more detail. when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode. when a development system is connected, it can pull both bkgd and reset low, release reset to select active background mode rather than normal operating mode, then release bkgd. it is not necessary to reset the target mcu to communicate with it through the background debug interface. 12.2.2 communication details the bdc serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external controller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb ?st at 16 bdc clock cycles per bit (nominal speed). the interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 156 freescale semiconductor when this timeout occurs is aborted without affecting the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and control register allows the user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or low level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles. figure 12-2 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. figure 12-2. bdc host-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 157 figure 12-3 shows the host receiving a logic 1 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 12-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 158 freescale semiconductor figure 12-4 shows the host receiving a logic 0 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target hcs08 ?ishes it. because the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 bdc clock cycles, then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 12-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 159 12.2.3 bdc commands bdc commands are sent serially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-?st using a custom bdc communications protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 12-1 shows all hcs08 bdc commands, a shorthand description of their coding structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 12-1 to describe the coding structure of the bdc commands. commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most signi?ant bit ?st) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in the target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target-to-host direction (from bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-target direction (for bdcbkpt breakpoint register) 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 160 freescale semiconductor table 12-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss read bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd read a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusive c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. report status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 161 the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to use for bdc communications until after it has analyzed the response to the sync command. to issue a sync command, the host: drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) removes all drive to the bkgd pin so it reverts to high impedance monitors the bkgd pin for the sync response pulse the target, upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal bdc communications): waits for bkgd to return to a logic high delays 16 cycles to allow the host to stop driving the high speedup pulse drives bkgd low for 128 bdc clock cycles drives a 1-cycle high speedup pulse to force a fast rise time on bkgd removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent bdc communications. typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 12.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware breakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this breakpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the ?st instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten) control bit in the bdc status and control register (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is disabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. 12.3 register de?ition this section contains the descriptions of the bdc registers and control bits. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 162 freescale semiconductor this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 12.3.1 bdc registers and control bits the bdc has two registers: the bdc status and control register (bdcscr) is an 8-bit register containing control and status bits for the background debug controller. the bdc breakpoint match register (bdcbkpt) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have addresses and cannot be accessed by user programs). some of the bits in the bdcscr have write limitations; otherwise, these registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents the ambiguous condition of the control bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be written by the write_control serial bdc command. the clock switch (clksw) control bit may be read or written at any time. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 163 12.3.1.1 bdc status and control register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 12-5. bdc status and control register (bdcscr) table 12-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ?typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ?this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ?if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ?when fts = 1, a breakpoint is requested whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagged. if this tagged opcode ever reaches the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ?clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 164 freescale semiconductor 12.3.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hardware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and con?ure the breakpoint logic. dedicated serial bdc commands (read_bkpt and write_bkpt) are used to read and write the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 12.2.4, ?dc hardware breakpoint . 12.3.2 system background debug force reset register (sbdfr) this register contains a single write-only control bit. a serial background mode command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ?when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force the target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a background command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status this status bit is set if a memory access command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically, the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not con?ct with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status this status bit is not used in the MC9S08QD4 because it does not have any slow access memory. 0 memory access did not con?ct with a slow memory access 1 memory access command failed because cpu was not ?ished with a slow memory access table 12-2. bdcscr register field descriptions (continued) field description 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 freescale semiconductor 165 figure 12-6. system background debug force reset register (sbdfr) 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. reset 00000000 = unimplemented or reserved table 12-3. sbdfr register field description field description 0 bdfr background debug force reset a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program. 4 datasheet u .com development support MC9S08QD4 data sheet, rev. 1 166 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 167 appendix a electrical characteristics a.1 introduction this section contains electrical and timing speci?ations. a.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits speci?d in table a-1 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table a-1. absolute maximum ratings rating symbol value unit supply voltage v dd ?.3 to +5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?5 to 105 c 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 168 freescale semiconductor a.3 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. a-2 solving equation a-1 and equation a-2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation a-1 and equation a-2 iteratively for any value of t a . table a-2. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?0 to 105 c thermal resistance (single-layer board) 8-pin pdip 8-pin nb soic ja 113 150 c/w thermal resistance (four-layer board) 8-pin pdip 8-pin nb soic ja 72 87 c/w 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 169 a.4 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. quali?ation tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.5 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table a-3. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulses per pin 3 machine series resistance r1 0 ? storage capacitance c 200 pf number of pulses per pin 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table a-4. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 v 2 machine model (mm) v mm 200 v 3 charge device model (cdm) v cdm 500 v 4 latch-up current at t a = 85 ci lat 100 ma 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 170 freescale semiconductor table a-5. dc characteristics (temperature range = ?0 to 105 c ambient) parameter symbol min typical max unit supply voltage (run, wait, and stop modes.) v dd 2.7 5.5 v minimum ram retention supply voltage applied to v dd v ram v por 1, 2 ? low-voltage detection threshold ?high range (v dd falling) (v dd rising) v lvdh 4.2 4.3 4.3 4.4 4.4 4.5 v v low-voltage detection threshold ?low range (v dd falling) (v dd rising) v lvdl 2.48 2.54 2.56 2.62 2.64 2.7 v v low-voltage warning threshold ?high range (v dd falling) (v dd rising) v lvwh 4.2 4.3 4.3 4.4 4.4 4.5 v v low-voltage warning threshold ?low range (v dd falling) (v dd rising) v lvwl 2.48 2.54 2.56 2.62 2.64 2.7 v v low-voltage inhibit reset/recover hysteresis 5v 3v v hys 100 60 mv mv bandgap voltage reference factory trimmed at v dd = 3.0v, temp = 25 cv bg 1.19 1.20 1.21 v input high voltage (2.7 v v dd 5.5 v) (all digital inputs) v ih 0.7 v dd ? input low voltage (2.7 v v dd 5.5 v) (all digital inputs) v il 0.3 v dd v input hysteresis (all digital inputs) v hys 0.06 v dd ? input leakage current (per pin) v in = v dd or v ss, all input only pins |i in | 0.025 1.0 a high impedance (off-state) leakage current (per pin) v in = v dd or v ss , all input/output |i oz | 0.025 1.0 a internal pullup resistors 3 r pu 17.5 52.5 k ? internal pulldown resistor (irq) r pd 17.5 52.5 k ? output high voltage ?low drive (ptxdsn = 0) 5 v, i load = ? ma 3 v, i load = ?.6 ma 5 v, i load = ?.4 ma 3 v, i load = ?.24 ma v oh v dd ?1.5 v dd 1.5 v dd ?0.8 v dd ?0.8 v output high voltage ?high drive (ptxdsn = 1) 5 v, i load = ?0 ma 3 v, i load = ? ma 5 v, i load = ? ma 3 v, i load = ?.4 ma v dd ?1.5 v dd 1.5 v dd ?0.8 v dd ?0.8 maximum total i oh for all port pins 5v 3v |i oht | 100 60 ma 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 171 figure a-1. typical low-side driver (sink) charactistics low drive (ptxdsn = 0), vdd = 5.0v, vol vs iol output low voltage ?low drive (ptxdsn = 0) 5 v, i load = 2 ma 3 v, i load = 0.6 ma 5 v, i load = 0.4 ma 3 v, i load = 0.24 ma v ol 1.5 1.5 0.8 0.8 v output low voltage ?high drive (ptxdsn = 1) 5 v, i load = 10 ma 3 v, i load = 3 ma 5 v, i load = 2 ma 3 v, i load = 0.4 ma 1.5 1.5 0.8 0.8 maximum total i ol for all port pins 5v 3v i olt 100 60 ma dc injection current (2), 4, 5, 6 v in < v ss , v in > v dd single pin limit total mcu limit, includes sum of all stressed pins |i ic | 0.2 5 ma ma input capacitance (all non-supply pins) c in ?pf 1 ram will retain data down to por voltage. ram data not guaranteed to be valid following a por. 2 this parameter is characterized and not tested on each device. 3 measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. 4 all functional non-supply pins are internally clamped to v ss and v dd . 5 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculat e resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd ) is greater than i dd , the injection current may ow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). table a-5. dc characteristics (continued)(temperature range = ?0 to 105 c ambient) parameter symbol min typical max unit 14 12 10 8 6 4 2 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 vol/v iol/ma ?0 0 25 85 105 typical low-side driver (lds) characteristics, vdd = 5.0v, porta 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 172 freescale semiconductor figure a-2. typical low-side driver (sink) charactistics low drive (ptxdsn = 0), vdd = 3.0v, vol vs iol figure a-3. typical low-side driver (sink) charactistics high drive (ptxdsn = 1), vdd = 5.0v, vol vs iol ?0 25 85 105 ?.6 1.2 1 1.4 0.8 0.6 0.4 0.2 0 vol/v 0 1 2 3 4 5 6 iol/ma typical low-side driver (lds) characteristics, vdd = 3.0v, porta 0 2.8 2.4 2 1.6 1.2 0.8 0.4 0 0 vol/v iol/ma 5 10 15 20 25 30 35 40 typical low-side driver (hds) characteristics, vdd = 5.0v, porta 105 ?0 0 25 85 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 173 figure a-4. typical low-side driver (sink) charactistics high drive (ptxdsn = 1), vdd = 3.0v, vol vs iol figure a-5. typical high-side driver (source) charactistics low drive (ptxdsn = 0), vdd = 5.0v, voh vs ioh ?0 25 85 105 0 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2 vol/v 4 0 6 8 10 12 14 typical low-side driver (hds) characteristics, vdd = 3.0v, porta iol/ma ?0 25 85 105 0 5.2 4.8 4.4 4 3.6 3.2 2.8 2.4 0 ioh/ma ? ? ? ? ? ? ? ? voh/v typical high-side driver (lds) characteristics, vdd = 5.0v, porta 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 174 freescale semiconductor figure a-6. typical high-side driver (source) charactistics low drive (ptxdsn = 0), vdd = 3.0v, voh vs ioh figure a-7. typical high-side driver (source) charactistics high drive (ptxdsn = 1), vdd = 5.0v, voh vs ioh ?0 25 85 105 0 3 2.8 2.6 2.4 2.2 2 1.8 1.6 ? ?.5 ? ?.5 ? ?.5 0 typical high-side driver (lds) characteristics, vdd = 3.0v, porta voh/v ioh/ma ?0 ?5 ?0 ?5 ?0 ? 0 ioh/ma 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 voh/v typical high-side driver (hds) characteristics, vdd = 5.0v, porta 105 ?0 0 25 85 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 175 figure a-8. typical high-side driver (source) charactistics high drive (ptxdsn = 1), vdd = 3.0v, voh vs ioh voh/v 3 2.8 2.6 2.4 2 2.2 1.6 1.8 ?2 ?0 ? ? ? ? 0 ioh/ma typical high-side driver (hds) characteristics, vdd = 3.0v, porta 105 ?0 0 25 85 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 176 freescale semiconductor a.6 supply current characteristics this section includes information about power supply current in various operating modes table a-6. supply current characteristics parameter symbol v dd (v) typical 1 1 typicals are measured at 25 c. max 2 2 values given here are preliminary estimates prior to completing characterization. unit run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz) 3 all modules except adc active, and does not include any dc loads on port pins ri dd 5 0.95 1.5 4 4 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. ma 3 0.90 1.5 run supply current 5 measured at (cpu clock = 16 mhz, f bus = 8 mhz) 5 all modules except adc active, and does not include any dc loads on port pins ri dd 5 3.5 5 6 6 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. ma 3 3.4 5 wait mode supply current 7 measured at (cpu clock = 16 mhz, f bus = 8 mhz) 7 most customers are expected to find that the auto-wakeup from a stop mode can be used instead of the higher current wait mode. wi dd 5 1.55 2.2 ma 3 1.50 2.2 stop2 mode supply current ?0 to 85 c ?0 to 105 c ?0 to 85 c ?0 to 105 c s2i dd 5 0.80 7.5 8 20 4 8 this parameter is characterized and not tested on each device. a 3 0.80 7.0 8 15 a stop3 mode supply current ?0 to 85 c ?0 to 105 c ?0 to 85 c ?0 to105 c s3i dd 5 0.90 8.0 8 25 4 a 3 0.90 7.1 8 20 a rti adder to stop2 or stop3 9 , 25 c 9 most customers are expected to ?d that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 3 v with f bus = 1 mhz. 5 400 na 3 350 na lvd adder to stop3 (lvde = lvdse = 1) 5 110 a 390 a adder to stop3 for oscillator enabled (irefsten = 1) 575 a 365 a 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 177 figure a-9. typical run idd vs bus freq(fei) (adc off) ridd/ma 10 8 6 4 0 2 0.00 0.50 1.00 1.50 4.00 3.50 3.00 2.50 2.00 bus/mhz typical ridd (vdd=5.0v, adc off) vs bus freq. 105 ?0 0 25 85 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 178 freescale semiconductor a.7 internal clock source characteristics figure a-10. typical deviation of dco output vs temperature table a-7. internal clock source speci?ations characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v and 3.0 v, 25 c or is typical recommended value. max unit average internal reference frequency - untrimmed f int_ut 25 31.25 41.66 khz average internal reference frequency - trimmed f int_t 31.25 khz dco output frequency range - untrimmed f dco_ut 12.8 16 21.33 mhz dco output frequency range - trimmed f dco_t 16 mhz resolution of trimmed dco output frequency at ?ed voltage and temperature 4 ? f dco_res _t 0.2 %f dco total deviation of trimmed dco output frequency over voltage and temperature 4 ? f dco_t 2 %f dco fll acquisition time 4,2 2 this speci?ation applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this speci?ation assumes it is already running. t acquire 1ms long term jitter of dco output clock (averaged over 2ms interval) 3 3 jitter is the average deviation from the programmed frequency measured over the speci?d interval at maximum f bus . measurements are made with the device powered by ?tered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. c jitter 0.6 %f dco ?0 ?0 0 20 40 60 80 100 120 140 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% ?.10% ?.20% ?.30% ?.40% ?.50% temp. /c deviation of dco output from trimmed frequency (8 mhz, 5.5v) deviation 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 179 figure a-11. typical deviation of dco output vs operating voltage 0.20% 0.15% 0.10% 0.05% 0.00% ?.05% ?.10% ?.15% ?.20% 3 2.5 3.5 4 vdd / v 5 5.5 6 deviation 4.5 deviation of dco output from trimmed frequency (8 mhz, 25c) 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 180 freescale semiconductor a.8 ac characteristics this section describes ac timing characteristics for each peripheral system. a.8.1 control timing figure a-12. reset timing table a-8. control timing parameter symbol min typical 1 1 data in typical column was characterized at 3.0 v, 25 c. max unit bus frequency (t cyc = 1/f bus )f bus 1 8 mhz real-time interrupt internal oscillator period t rti 700 1300 s external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized. t extrst 100 ns irq pulse width asynchronous path 2 synchronous path 3 3 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 t cyc ns kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 t cyc ns port rise and fall time (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?0 c to 105 c. t rise , t fall 3 30 ns bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ns bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 5 5 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 s t extrst reset pin 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 181 figure a-13. irq/kbipx timing a.8.2 timer/pwm (tpm) module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure a-14. timer external clock figure a-15. timer input capture pulse table a-9. tpm/mtim input timing function symbol min max unit external clock frequency f tclk dc f bus /4 mhz external clock period t tclk 4 t cyc external clock high time t clkh 1.5 t cyc external clock low time t clkl 1.5 t cyc input capture pulse width t icpw 1.5 t cyc t ihil irq/kbipx t ilih irq/kbipx t text t clkh t clkl tclk t icpw tpmchn t icpw tpmchn 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 182 freescale semiconductor a.9 adc characteristics table a-10. adc characteristics characteristic conditions symb min typ 1 max unit comment supply current adlpc = 1 adlsmp = 1 adco = 1 v ddad < 3.6 v (3.0 v typ) i ddad 110 aover temperature (typ 25 c) v ddad < 5.5 v (5.0 v typ) 130 supply current adlpc = 1 adlsmp = 0 adco = 1 v ddad < 3.6 v (3.0 v typ) i ddad 200 a v ddad < 5.5 v (5.0 v typ) 220 supply current adlpc = 0 adlsmp = 1 adco = 1 v ddad < 3.6 v (3.0 v typ) i ddad 320 a v ddad < 5.5 v (5.0 v typ) 360 supply current adlpc = 0 adlsmp = 0 adco = 1 v ddad < 3.6v (3.0 v typ) i ddad 580 a v ddad < 5.5v (5.0 v typ) 660 supply current stop, reset, module off i ddad <1 100 na ref voltage high v refh 2.7 v ddad v ddad v ref voltage low v refl v ssad v ssad v ssad v adc conversion clock high speed (adlpc = 0) f adck 0.4 8.0 mhz t adck = 1/f adck low power (adlpc = 1) 0.4 4.0 adc asynchronous clock source high speed (adlpc = 0) f adack 2.5 4 6.6 mhz t adack = 1/f adack low power (adlpc = 1) 1.25 2 3.3 conversion time short sample (adlsmp = 0) t adc 20 20 23 t adck cycles add 2 to 5 t bus =1/f bus cycles long sample (adlsmp = 1) 40 40 43 sample time short sample (adlsmp = 0) t ads 444t adck cycles long sample (adlsmp = 1) 24 24 24 input voltage v adin v refl ? refh v input capacitance c adin 7 10 pf not tested input impedance r adin 5 15 k ? not tested analog source impedance r as 10 (2) k ? external to mcu ideal resolution (1 lsb ) 10 bit mode res 2.637 4.883 5.371 mv v refh /2 n 8 bit mode 10.547 19.53 21.48 total unadjusted error 10 bit mode e tue 0 1.5 3.5 lsb includes quantization 8 bit mode 0 0.7 1.0 differential non-linearity 10 bit mode dnl 0 0.5 1.0 lsb 8 bit mode 0 0.3 0.5 monotonicity and no-missing-codes guaranteed integral non-linearity 10 bit mode inl 0 0.5 1.0 lsb 8 bit mode 0 0.3 0.5 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 freescale semiconductor 183 a.10 flash speci?ations this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the memory section. zero-scale error 10 bit mode e zs 0 1.5 3.1 lsb v adin = v ssa 8 bit mode 0 0.5 0.7 full-scale error 10 bit mode e fs 0 1.0 1.5 lsb v adin = v dda 8 bit mode 0 0.5 0.5 quantization error 10 bit mode e q 0.5 lsb 8 bit mode is not truncated 1 typical values assume v ddad = 5.0 v, temp = 25 c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 at 4 mhz, for maximum frequency, use proportionally lower source impedance. table a-11. flash characteristics characteristic symbol min typical max unit supply voltage for program/erase ?0 c to 105 cv prog/erase 2.7 5.5 v supply voltage for read operation v read 2.7 5.5 v internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz internal fclk period (1/fclk) t fcyc 5 6.67 s byte program time (random location) (2) t prog 9t fcyc byte program time (burst mode) (2) t burst 4t fcyc page erase time 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc mass erase time (2) t mass 20,000 t fcyc program/erase endurance 3 t l to t h = ?0 c to + 105 c t = 25 c 3 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale de?es typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 100,000 cycles data retention 4 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 years table a-10. adc characteristics characteristic conditions symb min typ 1 max unit comment 4 datasheet u .com appendix a electrical characteristics MC9S08QD4 data sheet, rev. 1 184 freescale semiconductor 4 datasheet u .com MC9S08QD4 data sheet, rev. 1 freescale semiconductor 185 appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering numbers for MC9S08QD4 devices. b.1.1 device numbering scheme b.2 mechanical drawings the following pages are mechanical speci?ations for MC9S08QD4 package options. see table b-2 for the document number for each package type. table b-1. device numbering system device number 1 1 see table 1-1 for a complete description of modules included on each device. memory available packages flash ram MC9S08QD4 4k 256 8 pdip 8 nb soic table b-2. package information pin count type designator document no. 8 pdip pc 98asb42420b 8 nb soic sc 98asb42564b mc temperature range family memory status core (v = ?0 c to +105 c) (9 = flash-based) 9 s08 qd xx (mc = fully qualified) x package designator (see table b-2 ) 4 approximate memory size (in kbytes) (c = ?0 c to +85 c) 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com 4 datasheet u .com MC9S08QD4 rev. 1, 9/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/paci?: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters that may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals? must be validated for each customer application by customer s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale s environmental products program, go to http://www.freescale.com/epp . freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2006. all rights reserved. 4 datasheet u .com |
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